What is the purpose of a power on reset circuit

[IanP]

Re: Power on Reset

Have e look at the DC and AC characteristics of the DS1232:
**broken link removed**
If you design a circuit that you expect to work without problems it should have parameters similar to these from the above data sheet and for them you should test your design..
And

Different Vdd rising time, different process, voltage and temperature corner

are part of these simulations..

 

[kib]

Re: Power on Reset

to add on
power on reset also makes sure that reset is released after the clock to the system is stable. normally the oscillators outputs will be stable after some finite time after power on

 

[ccw27]

Re: Power on Reset

It is often required that on-chip POR consumes low currents.
Notice simple RC POR might problematic if the power ramped too slowly.

Why does on chip POR need to consume low currents?

 

[ambreesh]

Re: Power on Reset

POR are used in tandem with µP. From a portable application point of view, you need to save your battery power.
POR' being majorly analog consume static power. They being supervisory circuits, cannot go into power down mode. Thus the power consumption is continious. One would want them to consume as less power as possible.
Hope it helps

 

[andy2000a]

Power on Reset

power on reset provide initial reset for chip,
another important signal is "Power OK"
or UVLO (under volt lock out) ,
many chip must be ensure power > some volt
just can work , like latch (2 invert feed back ltach) cell will work on Vcc < 3v
, if no power_ok signal maybe system board (motherboard) have leakage current
cause chip have unstable volt (maybe 1~2v) , I ever meet this issue becuase my
chip must latch some initial state . finally I add power_ok signal remove it .

some system have power_on_reset signal , but never use power_ok , like 8051 system , maybe 8051 will detect outside latch signal , no power_ok will cause 8051 get wrong message .

Added after 2 minutes:

by the way , power_ok is difficut design than Power_on_reset , becuase power_ok need accuracy volt for reference like Vcc=4.5v , but when power ramp_up at this time , bandgap maybe not work well will create "fake" power_ok signal .

 

[ambreesh]

Re: Power on Reset

Dear andy2000a,

Could you please elaborate on the fake power_ok signal generated at power ramp-up.
Would id show up in simulations across corners or is it to be observed during physical testing of the IC.

regards
ambreesh

 

[Tianlei]

Re: Power on Reset

For the power-ok signal. it neet to be hysteresis, otherwise the power-ok signal may switch when the supply is equal to the threshold.
the bandgap must work before the supply reach to the threshold.

Added after 2 minutes:

For the power-ok signal. it neet to be hysteresis, otherwise the power-ok signal may switch when the supply is equal to the threshold.
the bandgap must work before the supply reaching to the threshold.

 

[paladinzlp]

Re: Power on Reset

https://www.hardware-guru.com/BoardDesign\reset.htm