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What is snap-back ? (MOS analog design)

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tomph

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Snap-back ?!?

Can anyone please explain what snap-back is ? (in the MOS analog design)
Thanks a lot .
tomph
 

Re: Snap-back ?!?

In NMOS Tr., there is a paracitic NPN device under it (N+-Psub-N+). When the drain volatge exceed the NMOS's breakdown voltage, the NPN will turn on, then the drain voltage will be snap-back to small voltage and the current will be very large.

Best Regards,
Yibin.
 
Snap-back ?!?

First break down
Second break down
pls refer to the art of analog layout
 

Snap-back ?!?

The nmos or pmos transistor can be seen as biploar. For example nmos can be seen as paracitic NPN. When there is a bigger current(ESD), it will trigg the NPN turn on. This is first snap back. So generally, we use this character to ESD protection.
But with the current increase, the NPN bipolar will break down, that is second break down point. That will destroy the transistor permanent.
 
Snap-back ?!?

who have it

A. Amerasckera, M-C. Chang, C. Duvvury and S.
Ramaswamy, “Modeling MOS Snapback and Parasitic Bipolar
Action for Circuit-Level-ESD and High-Current simulations”, in
Proc 34th IRPS, pp. 318-326, 1996.
 

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