what is about symbol library in Design-vision?

[kermit]

synopsys .slib

Recently i want to transfer my synthesis tool from pks to dc.but in design-vision , i cant understand an option --symbol library .
I just wonder what is symbol library,and where i can get it .
maybe i may compile a library use library compile,maynot I?


pls give me some advice!

 

[wadaye]

Hi kermit:

Symbol library is used by design-vision/design-analyzer to display a

symbol accroding the gate.If you have experience of Debussy, you can

understand it quickly.

You can get a symbol library from the Asic Vendor or you can generate a

symbol library yourself.

Library compiler is used to convert the .lib to .db.

wang1

 

[giggs11]

Actually, Library Compiler has to be used to convert both the tech.file(.lib) and symbol library(.slib) to .db and .sdb respectively.

 

[kermit]

wadaye:

You can get a symbol library from the Asic Vendor or you can generate a symbol library yourself.

How to generate a symbol library by myself? can you give more detail information about this? Or you can give me some reference documents about this in SOLD!


giggs11

Actually, Library Compiler has to be used to convert both the tech.file(.lib) and symbol library(.slib) to .db and .sdb respectively.

where can i get symbol library .slib?Vendor provide?
But I can't find this in UMC 0.25 CMOS library.

 

[jaxshai]

wadaye:

You can get a symbol library from the Asic Vendor or you can generate a symbol library yourself.

How to generate a symbol library by myself? can you give more detail information about this? Or you can give me some reference documents about this in SOLD!


giggs11

Actually, Library Compiler has to be used to convert both the tech.file(.lib) and symbol library(.slib) to .db and .sdb respectively.

where can i get symbol library .slib?Vendor provide?
But I can't find this in UMC 0.25 CMOS library.

If foundry do NOT provide slib, you might find it in synopsys CD.

 

[kermit]

jaxshai:

If foundry do NOT provide slib, you might find it in synopsys CD.

I dont have synopsys CD, I just download install file from synopsys ftp. Can you give me more information about this,such as the content in this CD ?!!

 

[jaxshai]

One Slib library , for your information

 

[kermit]

Thanks a lot ! !!!
I know something about symbol library!!!
I find this on synopsys website:

How to convert an EDIF schematic symbol library to synopsys .slib


Question:


How do I convert an EDIF schematic symbol library to synopsys .slib?
Answer:


dc_shell> read_lib EDIF_filename -format edif -symbol symbol_filename.slib

EDIF_filename is the EDIF file containing symbol information generated by EDIFOUT.

symbol_filename.slib is the ASCII file that will contain the Synopsys
version of the symbol library.

In addition, set all neccessary edifin variables( refer to EDIF
Interface User Guide, and all edifin_lib variables):

edifin_lib_route_grid = 1024
1024
edifin_lib_in_port_symbol = "ipin"
"ipin"
edifin_lib_out_port_symbol = "opin"
"opin"
edifin_lib_inout_port_symbol = "iopin"
"iopin"
edifin_lib_in_osc_symbol = "iosc"
"iosc"
edifin_lib_out_osc_symbol = "oosc"
"oosc"
edifin_lib_inout_osc_symbol = "oosc"
"oosc"
edifin_lib_logic_0_symbol = "gnd"
"gnd"
edifin_lib_logic_1_symbol = "vdd"
"vdd"
Former article name: METH-844

 

[kermit]

another article about slib:

Converting modeldb to ITS (.slib) Models


Question:


Can PathMill convert an existing modeldb to a ITS (.slib) timing model?


Answer:


Yes, you can do this in two ways.

1. Using PathMill Plus to read in the modeldb file and then write out the same
model in ITS (.lib) format.

a. In PathMill Plus batch mode:
1) Include these TCL commands in your command file to read your modeldb file
and then write it out in the format (STAMP | ASCII | ITS) you desire.

read_model -format modeldb -name { model.modeldb }
write_model -format ITS -name its_model_name

2) Run PathMill Plus (converts model).

If you happen to have more than one model, you can also merge these into a final
ITS (.lib). In your command file include these commands to read, select paths,
and write out the model:

read_model -format modeldb -name { model1.modeldb }
read_model -format modeldb -name { model2.modeldb }
mark_model_paths -select -mode MODE1 MODE2
write_model -name ALL -format ITS -modes MODE1 MODE2

Note: It is assumed that model1.modeldb and model2.modeldb above are generated
with a specific mode (MODE1 and MODE2, respectively). The "-select" option
selects paths in nonoverlapping fashion. The write_model command writes all
modes to a single database in ITS format.

b. In PathMill Plus mg or model editing (shell) mode (invoke PathMill -mg
shell):

shell> pathmill -plus -mg -tcl
mg>read_model -format modeldb -name model_name.modeldb
mg>write_model -format ITS -name its_model_name

In mg mode, you can also use the previously described methods to merge models
into a final ITS (.lib) when you have more than one model to be read.

2. The second way is to generate an ITS (.lib) model for a dummy module
containing only the model you want to convert. For this conversion, we'll
use the build_model config command with options "syn_lut syn_its" to create
a ITS (.lib) model from the .modeldb file.

a. Read the circuit containing the modeldb (for example, adder.modeldb); for
example,

pathmill -nspice model.sp netlist.top \
-c cfg \
-o adder \
-x

model.sp contains a dummy module declaration and netlist.top is tx-level
netlist for the block.

.subckt top port-list...
X1 port-list... adder
.ends

Where "adder" is the prefix in timing model name we have.

Also, you will need to use these config commands to set netlist control
options to read the modeldb and generate a new ITS model in PathMill;
for example,

netlist_ctrl_opt prefer_model_port_map:"adder.modeldb"
build_model model_name syn_its syn_lut charfile ....

Note: Here you would also provide characterization data. The charfile used
in this run should match the one used when creating the original modeldb file.
If this data is not provided for a given input or output port:

* PathMill finds the input slope from the default_rf_time and the output
capacitance from the sink_node commands.

* Characterization is performed by varying slope or capacitance (0.5, 1, 2)
times the default_rf_time and the output capacitance from the sink_node
commands.


Note: If your models are in SASCII format, you will need to convert them to
modeldb format by using PathMill. Different versions of PathMill may have
different binary formats.

You will get a WARNING message if the binary file is incompatible with the
version you're using. To convert timing databases from major release to release,
use the same PathMill version that was used to generate the binary database to
convert it to ASCII format first. Then use current version of PathMill to
convert from ASCII to binary format. To convert from ASCII to binary format
or visa versa, use the following options:

pathmill -ascii2modeldb model.ascii model.modeldb
pathmill -modeldb2ascii model.modeldb model.ascii

BTW I find this slib or sdb on symbol directory !

 

[srini.pes]

Respected all..........
Whats the difference between link library, target library & symbol library
I have library files with extensions ".lib" , ".lef" , ".tf"
out of these which one is my target, link and symbol library
I dnt have any resource here to clarify these things
Please help me and clarify my doubt
Thanks

 

[phoenixpavan]

Hi Srini,

Target library is one to which you want to implement your design in.
Link Library is for resolving the references in your design
Symbol library is for schematic information of the gates that are present in your netlist in case you are using Design Vision

You need to convert your .lib files to .db format for using in your synthesis process

I strongly suggest you to go through Design Compiler user guide for more understanding of these issues...

PS: Please do not reopen old threads...search the forum to find out whether your query had already been posted and answered by someone.

Cheers

 

[srini.pes]

Thank you so much pavan
But i am in confusion while deciding these three...
first i need to convert these files into .db and .sdb na
For those which file refrs to target and which refers to link and to symbol
please clarify those
waiting for u r reply

 

[phoenixpavan]

Your ASIC vendor must provide a DC-compatible technology library for synthesis. The Target Library is the library used by Design Compiler for building a circuit.

set target_library my_tech.db so in this my_tech will be the one of your choice based on your requirements.

So it works the other way round...the lib file which you choose to use with set_target_library will be your target library..Its not that you there are separate trget libraries listed.

For link set link_library {* my_tech.db} * refers to the DC memory. You can also other db files also along with mem and target lib.

Helpful??

 

[srini.pes]

Thank u pavan
but my doubt was i have tsmc90 library in that may be am having the target library , is it correct
and what abt link library and symbol library
Symbol lib-->> schematic info of the gates that are present in your netlist...

 

[phoenixpavan]

Yes you can choose tsmc90 lib as your target
you have the dc memory and tsmc90 as your linklibrary..
For symbol library check for the extension .sdb and set it

cheers

 

[srini.pes]

Thank you pavan for u r quick response
As u r suggestion, i will set this target library as my tech TSMC90(.lib) file but i need to convert this to .db na
how to convert this to .db file
and i dnt know about the dc memory, is it like "*" + target.db (as given in the design vision pdf)
and i have one .sdb file i will arrange it to that
please clarify how to change .lib to .db
Thank u soo much

 

[phoenixpavan]

You need a library compiler to convert your .lib files to .db

You can use read_lib command to convert but a lc license is required

 

[srini.pes]

Ya
i have generated the .db file for my technology library .lib file
then i need link library.............
one more thing i want to ask, if we write in a tcl file all these things then it will automatically set to all libraries

 

[phoenixpavan]

Absolutely...

All the best

 

[srini.pes]

thanks pavan jee
then what about link library and symbol library