What are the methods for laying out differential pair/node in high speed application?

[protonixs]

Re: differntial pair

The idea of capacitive coupling as suggested by srieda might be correct as the common mode noise gets rejected.
But can anybody explain in detail, how putting dummy metal between the pair helps ?

Thanks

--cmos_dude

the dummy metal acts as the common node of the parasitic capacitance bet the diff pair.
theredore, the parasitic capacitance will be seen as series from the first input to the common node and from the common node to the other input.

 

[stuck_adc]

Re: differntial pair

the lines should be symmetrical no doubt..................but what i have seen in the case of sense amplifiers..........the designer provides a range for the paracitic capacitances of the 2 lines.

in my case the difference between the parasitics capacitance the 2 lines should not be more then 1%..........any way the layout designer have to follow this range and at the same time try to keep the parasitics as much small as possible.


the matching part is done to get this range of 1%.....


hope this helps.

 

[hazemafify]

differntial pair

i think in high freq you must take care about symmetric more than matching

 

[forkschgrad]

Re: differntial pair

i think in high freq you must take care about symmetric more than matching


can you further explain or differentiate symmetric to matching? tnx.

 

[test_out]

differntial pair

hic, layout differential signals, I am facing it now. My problems is that I have many diferential signals pairs (signals and also the clocks). So difficult to make it symmetric and matching((. help meeeeeee

 

[jecyhale]

Re: differntial pair

If it operate with RF signal and large signal, the load matching and input parasitic capacitor is most important.

 

[analayout]

Re: differntial pair

Hi,

Differential input you can put shielding so that you can ground the couoling
capacitance.

Regards,

Analayout.