voltage delay mechanism question

[yefj]

Hello, I was given the following circuit, somehow its suppose to open one voltage after the other.
I suppose its opening Vd+ later then the others.The inputs are tottaly DC.
Somehoe there is RC mechanism which will delays the opening of maybe Q1.
probably i am tottaly wrong but this this what its supposed to do.
Is there some more practical intuitions regarding how this circuit works?
Thanks.

 

[BradtheRad]

Hello Bradtherad,The key thing here is to slow down some how the rate at which Veb is getting increased.
I have tried to Sweep across many many values of capacitance the Veb value rises with absolutly no change with respect to the capacitance as shown below.
Where did i go wrong?
Ltspice file is attached .
Thanks.

It looks as though you're now testing a PNP type. That's okay but you should reverse the positions of the RC components. It's all in the steps to building the circuit that is usable in negative polarity and then a second circuit that is usable in positive polarity.

I wonder about the power supply being labelled 'pulse'. In simulation you only need to start at Time=0, make the supply continual DC, then observe voltages for 3 seconds. Come to think of it, it's just the same with hardware.

 

[D.A.(Tony)Stewart]

Stop using OP90 with illegal Vin conditions, then trust a slow simulator output

Hello Bradtherad,The key thing here is to slow down some how the rate at which Veb is getting increased.
I have tried to Sweep across many many values of capacitance the Veb value rises with absolutly no change with respect to the capacitance as shown below.
Where did i go wrong?
Ltspice file is attached .
Thanks.
View attachment 193590

> Where did i go wrong?

Everywhere !

1. The source risetime Tau=R1C1, on C1 is measured in seconds so it will always be 0V in all your plots assuming no load...but,
2. The load impedance Zin = R12+ hFE R2 = 1k+100*15 = 2k5 is far less source R1||C1 but Tau is still far too long to make any visible difference,
3. This looks like an instant ON and very slow OFF switch with up to a 1V drop
4. C1 must be on the high side to have an initial OFF state.
5. A PNP emitter follower makes a poor high side switch if you had a pull down on base.
6. A low side NPN switch or Nch low side or Pch FET high-side is more effective.

Inverting single Transistor configurations are always better switches NOT voltage followers.

Controllable risetime but inefficient switch

--- Updated Sep 3, 2024 ---

Bad design

--- Updated Sep 3, 2024 ---

Better time delay design with 20 to 40 ns depending on Vt tolerance. but 50% accuracy.

RdsOn = 10 mohm in both cases.

--- Updated Sep 3, 2024 ---

but none of these time delays work if your power supply rise time is slow

--- Updated Sep 3, 2024 ---

You must control or specify your supply risetime under all conditions so that it does not affect any circuits using Vdd or Vss for power on critical power enable pulses. The supplies should be stable before activating controlled outputs.

Normally this is done in all PC MOBOs using DC OK signals that verify all supply voltages and hold Reset to CPU until all OK.
Any following dropouts from DC OK cause power to be shut down, waiting for an AC recycle or POR power-on reset.

Here is a complicated way that forces a time delay slower than expected supply settling time and compares the delay of charging current with a 0.5V diode reference voltage which also has a time delay. It is complicated but independent of Vdd voltage as it only detects the decay of the charging 10 nF capacitor. Here the delay was 500 ns using the 500 mV Vref from the diode. (456 mV)

There are many ways to detect DCOK including under/overvoltage window comparators or Op Amps that can sense near ground.

If you knew the Vss source was 50 us, then the detector caps would be scaled to reach > 95% of Vdd or 99% or 99.9% if you wanted just by choosing the settling current level. An additional diode might seem redundant until you have a line dropout. to protect the device from excess Vin. The comparator output voltage is your choice depending on its source.

It all depends on your expectations of disturbances and design specs.

 

[yefj]

Hello In post 60 , I made the left side of the circuit working .
Looking at the faulty schematics of post 60.
Why they used opamp for creating Vg of -2.5V ?
What is the general logic of the right side ?
Thanks .

 

[D.A.(Tony)Stewart]

Hello In post 60 , I made the left side of the circuit working .
Looking at the faulty schematics of post 60.
Why they used opamp for creating Vg of -2.5V ?
What is the general logic of the right side ?
Thanks .

Only Kirchoff laws to obtain some computed bias current to get a voltage within 10% tolerance based on datasheet Vz at 5 mA

Op60 may work but is not very precise or fast.

 

[yefj]

Hello Tony, We have 12V which will produce +5V for drain of the TGA2227 amplifier.
I have the -12V which we can create -2.5 for the gate(earlier then Vdrain)
I can use LM1084 to do direct convertion of 12 to 5V.
What could be the reason to use an OPAMP like they did?
Thanks.