voltage delay mechanism question

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yefj

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Hello, I was given the following circuit, somehow its suppose to open one voltage after the other.
I suppose its opening Vd+ later then the others.The inputs are tottaly DC.
Somehoe there is RC mechanism which will delays the opening of maybe Q1.
probably i am tottaly wrong but this this what its supposed to do.
Is there some more practical intuitions regarding how this circuit works?
Thanks.

 

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As you can see in the photo from LTSPICE and the graphs, I have tried to pass the voltage from P12 only when M12 signal is going from 0 to -12. However my Q1 is always conducting and Q3 is always conducting.Is there a way to close Q1 and Q3 when M12 is 0 and open Q1 and Q3 when M12 is -12V using a BJT logic?
Thanks.

 

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As an alternative could you give me such circuit as Brian said so I would learn how to do it with BJT’s?
 

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yefj said:
Is there a way ... using a BJT logic?
Click to expand...
There was a time when BJT was all we had. You wish to step through a series of events. Each event is triggered by success of the preceding event. Also direction of voltage change. All those resistors have to be adjusted to the proper values. It's a tall order to fill, to result with the necessary voltage at one node.

An alternate method is to build a cascade of transistor delay turn-on networks, chaser style. Each section energizes the next section.
 

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Hello So the purpose is to compare one pulse to the other and see which one got the rising edge first .
What component do you reccomend to use for this purpose ?
Thanks .
 

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Hello Tony, this is exactly what is happening in my simulation its running very slow when i put this OP90.
What are the ranges allowed for the inputs of the OP90 in the inverting and non inverting ?
its not clear in the table below.

--- Updated ---

danadakk said:
For some supercilious is a necessary and apparently necessary state of mind.
Click to expand...
Hello Dana yes you are tottaly correct, could you present with some comparator based circuit which performs this function?
Thanks.
 
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Hello , The circuit below outputs P12 when M12 turns 0 to -12V.
I'll be happy to know what to do next by Brians logic , Of what he said below
Thanks.
"This is often done in MOS amplifiers to ensure the gate voltage is present before the drain voltage or vice versa, depending on the design so the device can't start up at maximum current if voltage on the gate isn't present first. We really need to know what the rest of the schematic is to be sure."




--- Updated ---

UPDATE 2:
Thank you for your patients.
So the left side of the junk schematics i was given checks m12 pulse comes first and the P12 pulse.
What about the right side of it?
from data sheet.
Vd=8V
Vg=-2.5V
Vc=4V
They took the output of PNP and put it as a positive suppy to the opamp.
Also they used resistor voltage divider to use as positive input of OP90.
OP90 is being used as a comparator here but i am not sure what is the logic of this thing?
Thanks.

--- Updated ---

UPDATE 3:
Tony said OP90 is a bad choise.
What alternative you reccomend?
Thanks.
 
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Did you not get the message when I said the OP90 will never work if the inputs rise to Vdd (+V)? They must have NPN inputs not PNP or Nch not Pch.
Although rare in BJT's it will work with R2R input CMOS types.

The slow response to LTSpice is due to something misbehaving, without proper bias.

e.g. Do you understand why below fails with PNP?

 

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Hello Tony , Yes because Veb of PNP is not enough to open the PNP, so the current is not running threw the PNP unlike NPN.
How did you see it ?
Given the schematics below where do i put the voltages to see that this OPAMP will not work?
What alternative OPAMP you reccomend?

Thanks.
 
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I already told you what to search for and told you the reason why Input > 13.5 on +15=V+ or within 1.5V of V+ will fail. The spec does not reach the +ve rail for this design to work.
Another design might not have this failure. All the recommended I/O specs MUST BE MET in EVERY DESIGN.

 

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yefj said:
As an alternative could you give me such circuit as Brian said so I would learn how to do it with BJT’s?
Click to expand...
Capacitor to gnd biases NPN. Cap charges through resistor in order to delay turn-On of NPN. Time frame is 1 second. This simplified example needs large cap value.
By making a darlington pair you can get by with a smaller cap.

The same method can work in negative polarity by changing the NPN to PNP, and inverting polarity of the supply.

 

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Yes i understand that input must be DC at least lower by 1.5 V then the power rail.
I know the schematics i got is tottaly wrong so i am just trying to collect the principles.
In the marked area by red arrow SZBZX84C4V7ET1G we have a zenner diode with a resistor.
If output of the opamp is around 12V why after the zener its 1V.
What is the mathematical logic which zener plays with the resistor giving us 1V at the output?
Thanks.







--- Updated ---

Hello Brad , Very good principle , I reaaly dont want to go back to the original faulty circuit.
The circuit below is simulation tested for the ability to pass P12 only when M12 pulse already came.
Suppose I will not put the delay on the -12V source as shown below.
How do you reccomend to make the delay using the capacitor method you shown in the circuit below?
Thanks.

 

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  • try3 (3).zip
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yefj said:
How do you reccomend to make the delay using the capacitor method you shown in the circuit below?
Click to expand...
This is the best I could do to imitate the timing diagram in post #37.

Delay lasts for a second to the negative polarity (PNP). Then load #1 receives power. This starts a delay in the positive region. Then load #2 conducts. Time frame is 3 seconds. More experimenting is needed to achieve the correct voltages.

This is not necessarily your optimum solution. It's just a different approach to the sequential start-up.

 

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Hello Brad, I have tried to recreate the simulation you showed in LTSPICE.
Its exactly as you presented in post #51,
Why i get a straight line instead of the delayed responce?
Thanks.
 

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yefj said:
Hello Brad, I have tried to recreate the simulation you showed in LTSPICE.
Its exactly as you presented in post #51,
Why i get a straight line instead of the delayed responce?
Thanks.
Click to expand...
By all means play with component values. As a matter of fact I tested several variations. I used the default transistor gain 100. (However the 2N2222 can have higher gains in real life.) Of course resistor values are flexible and you can customize your network to yield different responses on power-up.


Link below runs my schematic in Falstad's animated interactive simulator:

tinyurl.com/27jwp863

Select Toggle Full screen (under File menu).
Change component values by hovering and turning mouse thumbwheel.
 
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Hello, I have made an LTSPICE file and photo in the attached zip file. I can see only a very tiny curving on the output.
The voltage signal is not shifter at all with respect to the output signal.
Is there intuition i could use to see this shift?
Thanks.

 

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As the run begins the capacitor should be 0V (discharged or nearly discharged). You may have to set it that way deliberately. I did not include a discharge resistor across the capacitor which resets it when turned off.

Seeing the scope labels I can't be sure which voltage they measure. The 15Ω resistor should be the load. The NPN should admit increasing current through it during the space of a second.

'Intuitive knowledge' about this sort of capacitor-based delay comes from observing a basic RC network:

Timeframe is 1 second. A reset is marked by the bold vertical grid line.
Link which loads above schematic in Falstad's simulator:

tinyurl.com/2cov4nv7
 

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Hello Bradtherad,The key thing here is to slow down some how the rate at which Veb is getting increased.
I have tried to Sweep across many many values of capacitance the Veb value rises with absolutly no change with respect to the capacitance as shown below.
Where did i go wrong?
Ltspice file is attached .
Thanks.
 

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  • try3 (2) (1) (1).zip
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Update :
It works as shown in the attached photo and LTSPICE file
Regarding the right side of the faulty circuit i was given
Do you see what could be the role of the OPAMP for outputing the desired negative -2.5V voltage needed by the Vg of the TGA2227?
Thanks.

 

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  • schem.zip
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