voltage delay mechanism question

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Hello, I was given the following circuit, somehow its suppose to open one voltage after the other.
I suppose its opening Vd+ later then the others.The inputs are tottaly DC.
Somehoe there is RC mechanism which will delays the opening of maybe Q1.
probably i am tottaly wrong but this this what its supposed to do.
Is there some more practical intuitions regarding how this circuit works?
Thanks.

 

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Hello Dana , Brian In post 18# sugested a theory regarding my circuit.
Could you say the logic of the inner parts?
How gradually increasing one input makes a sequence?
How the parts work together?
Thanks.
 

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I cannot tell what the input side to the PNP pass transistor base circuitry is
doing. Seems like nothing.....




Regards, Dana.
 

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Q1 does not conduct because it assumes the supplies are equal within 10% in rise time and amplitude but never checks if they are in spec.
V1= |V2| 10k to -12V and 12k to +12 to Q1b.

U1a may have Vin+ common mode issues pulled up to V+ and needs specs for differential input specs. for the output between V- and Zener voltage.
 

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As I thought, all you have to do is ensure Vg is present before Vd is applied, otherwise the current drawn from Vd may cause damage. The same process could just as easily be done with a comparator, the present circuit uses the Zener diode to ensure one rail is up enough before the other.

Personally, I would adopt the MCU approach, it is simpler, more predicatable and cheaper.

Brian.
 
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Hello Brian, My goal is to learn this circuit and to develop intuition regarding how such different components will function.
as you said I have to ensure Vg is present before Vd is applied.
I have three input pins creating Vd Vg and Vc.
which input should I increase gradually so I will see this effect?
Thanks.

 

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You cannot understand until you fully understand every component in every possible condition. Learn all the basics.
Once you understand, analyze any schematic by looking at how the 1st part reacts then the next etc

Now what happens here when the input on U1A when both inputs are within 1.5 V of Vd+ ?
This is called violating the Vcm input range in the datasheet.
 

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Hello ,So as Brain suggested, In my simulation what input should i graudally increase to see the effect?
Thanks.
 

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You can reduce V- by 2V to 10V and see what happens

My comment has to do with another design flaw.

Nothing will be guaranteed if the input requirements are not met.
It might have inverted logic output when your input range is violated. You have it in a cutoff condition. A simulator cannot indicate all the effects of mfg tolerances within an IC. LTspice might even run slow, struggle or belch out bad results.

The use of an OP90 in this design is faulty with P type inputs on any Op Amp. This requires a comparator or Op Amp with N type inputs so it can operate near the V+ supply input.
 
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I'm looking at Q2 Q3 (post #1). They're cross-biased as if to resemble an SR flip-flop. Then also negative polarity is present. Possibly their purpose is to delay conducting bias to Q1 until both positive and negative supplies come through the connector.
And to halt conducting if either positive or negative is lost.
 

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Hello Dana, given your simulation you say that the DC inputs cannot be simultaneous for this circuit to work as Brian said?
We have to put +12V -12V at different times for this to function by Brian presented idia?
Brian said:
This is often done in MOS amplifiers to ensure the gate voltage is present before the drain voltage or vice versa, depending on the design so the device can't start up at maximum current if voltage on the gate isn't present first. We really need to know what the rest of the schematic is to be sure
 

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The sims in post #31 show only when both supplies are up do we get the pass transistor/load
turned on.
 

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Hello Dana,So the heart of the idia are these BJT transitors.
I have found a fault also with the biasing of Q2.
I just need to understand the logic of these transistors in inplementing the idia.
Basickly Q3 is opening Q1.

Brian sayed we can make a sequencer out of this circuite if I change gradually M12(-12V)? correct?
Also this output goes into opamp.
Could you describe how can I make this circuit to resemble a sequencer?
what is the analog logic in creating a sequencer in here?
Thanks.
 

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The "circuit" you posted in post #1 simply inadequate to do all the above.

1) Based on a debounced switch or logic input turn on a -4V supply to gate

2) For a current limiter circuit set it to limit at 100 mA. Could be a control
loop that ramps a DAC output V until it measures 100 mA in drain. Could be
a VCIS.

3) Now switch on a 50V supply to drain circuit.

4) Now loop and ramp Vg until you measure 50 mA in drain

5) Now set drain circuit current limiter to a V value that limits at 1.5A. The VCIS.

6) Apply RF

Obviously this is a state machine, best and easiest done with a micro, one would
add fault conditions to turn off the supplies. A micro with a DAC (or use its PWM for a DAC),
and A/D, some analog muxing to measures Vgate, and current shunts.

5) Now output a RF

This is a tad overkill but is a one part solution (an example project) :



Note the part has OpAmps to create the VCIS, and lots of other stuff on it.

The wizard used to setup sequence :



Or use a ATTINY85 like part and do some coding.
 
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Hello Dana , regarding creating a sequencer is a whole other story.
With your help i understood that this circuit( Is very very faulty) but this circuit structure is supposed to check the sequence .
Given the BJT transistors which are valves,could you reccomend a basic sturture so i could start over and implement this sequence checker?
Thanks.


--- Updated ---

Hello Brian , Can you please show such circuit as an example so I could simulate it and see what exactly the analog mechanism?
(the circuit i was given is very faulty and i want to start over)
Thanks.
 
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I think you need to consider getting professional help in the form
of a consultant to do a ground up design here.

Regards, Dana.
 

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now include the input conditions and output load regulation error.
 

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