voltage delay mechanism question

[yefj]

Hello, I was given the following circuit, somehow its suppose to open one voltage after the other.
I suppose its opening Vd+ later then the others.The inputs are tottaly DC.
Somehoe there is RC mechanism which will delays the opening of maybe Q1.
probably i am tottaly wrong but this this what its supposed to do.
Is there some more practical intuitions regarding how this circuit works?
Thanks.

 

[barry]

I didn’t spend a lot of time trying to understand this schematic, but my first impression is: it’s garbage. Why use three 1K in parallel instead of one 330? Why use a dual-diode package when you’re only using one of the diodes? Why use the negative supply to bias Q3? And I don’t see how it’s going to “open one voltage after the other.”

But I also have to ask, have you tried simulating this? Why not?

 

[yefj]

I didn’t spend a lot of time trying to understand this schematic, but my first impression is: it’s garbage. Why use three 1K in parallel instead of one 330? Why use a dual-diode package when you’re only using one of the diodes? Why use the negative supply to bias Q3? And I don’t see how it’s going to “open one voltage after the other.”

But I also have to ask, have you tried simulating this? Why not?

Hello Barry, I have this circuit just to learn principle I want to see the general logic before i simulate it.Maybe you saw something similar,So i could learnand simulate it?
Thanks.

 

[D.A.(Tony)Stewart]

I didn’t spend a lot of time trying to understand this schematic, but my first impression is: it’s garbage. Why use three 1K in parallel instead of one 330?

But I also have to ask, have you tried simulating this? Why not?

3x 1k from 12 V =436 mW shared by 3 *1/4 W rating is 58 % is a good design for T & $ reasons, not garbage

but using both diodes has a lower Rzk than 1.

The OP90 and R3 has very slow slew rate.

I am always amazed that @yefj never follows any design specs, rather hit and miss trying to understand performance from random attempts to make a switch amplifier/ sequencer.

 

[barry]

3x 1k from 12 V =436 mW shared by 3 *1/4 W rating is 58 % is a good design for T & $ reasons, not garbage

but using both diodes has a lower Rzk than 1.

1) So, based on your calculation, you think this circuit is designed to provide 12Volts into a dead short?
2) A 1W resistor costs less than three 1/4W resistors, in money, PCB real estate, assembly costs.
3) I have no idea what you mean about "using both diodes". They are NOT using both diodes, which was my point.

 

[D.A.(Tony)Stewart]

1) I assumed it was repetitive pulsed into a large capacitance, but got your point.
2) Disagree in volume ,agree for 1. unless you add up the cost of ordering 1 new part when you already have a reel of the std parts
3) Rather than criticizing using only 1, I recommended a solution to use 2 to improve load regulation with two Rzk in ||.

 

[yefj]

Hello Tony , If I understand correctly the zenner diode make the delay between output signals ?
Or there is no way this circuit found some sort of delay between DC signals ?
Thanks.

 

[D.A.(Tony)Stewart]

Hello Tony , If I understand correctly the zenner diode make the delay between output signals ?
Or there is no way this circuit found some sort of delay between DC signals ?
Thanks.

Do you know how to compute RC delay?

Mr Zener will forgive you this time only.

 

[yefj]

Hello Tony , using which capacitors Q1 open in delayed form ?
Thanks .

 

[D.A.(Tony)Stewart]

Hello, I was given the following circuit, somehow its suppose to open one voltage after the other.
I suppose its opening Vd+ later then the others.The inputs are tottaly DC.
Somehoe there is RC mechanism which will delays the opening of maybe Q1.
probably i am tottaly wrong but this this what its supposed to do.
Is there some more practical intuitions regarding how this circuit works?
Thanks.

View attachment 193354

From what I understand, it does not do what you want without some minor changes, but I won't help until you learn to makes specs using a pencil and paper napkin. Then after you can learn to do it professionally like a datasheet summary.

 

[yefj]

Hello Tony , what do you mean to make specs?
Could you elaborate what does it mean ?
Thanks .

 

[D.A.(Tony)Stewart]

It means to define to transfer functions by plots, tables and specs. Plot all I/O's and load specs

 

[yefj]

Hello Tony Input is +-12V as shown in the schematics.
This circuit is supposed to be a sequencer for TGA2227 .
outputs:
Vg=-2V Vc=+4 and Vd=8V.
I dont know what load each pin will see from the TGA2227.
Also there is a good chanse the circuit schematics will not produce the desired voltages.
Hope I answered the requirement.

TGA2227-SM - Qorvo

www.qorvo.com

 

[D.A.(Tony)Stewart]

Try a timing diagram with a block diagram for all inputs and outputs.
- you must specify the load current and capacitance by your design choices to determine slew rate and delay time with any sort of logic.

 

[betwixt]

I think the term 'delayed' is being misunderstood. It isn't a time delay as such, its a sequence as the input voltage increases. The delay is set by the rise time of the input voltage not a predetermined time interval.

Brian.

 

[D.A.(Tony)Stewart]

- many unknowns like the input/output supply rise time, recycle time, load current, pulse rate etc

 

[yefj]

I think the term 'delayed' is being misunderstood. It isn't a time delay as such, its a sequence as the input voltage increases. The delay is set by the rise time of the input voltage not a predetermined time interval.

Brian.

Hello Brian sorry for the misunderstanding .
So you say I have a constant input and the output at certain pins changing as the time goes ?
If I am correct could you please say how it’s happening ?
Thanks .

 

[betwixt]

No, I'm saying the output switches at different input voltages. Sometimes this has to be done so that one supply doesn't 'overtake' another as they rise or fall.
When a step voltage is applied at the input, the outputs will change simultaneously, excepting for the tiny delays within the ICs and stray capacitance/inductance, but if the voltage rises slowly, the outputs will switch in sequence. Try a simulation and slowly increase the input voltage to see how the outputs change.

This is often done in MOS amplifiers to ensure the gate voltage is present before the drain voltage or vice versa, depending on the design so the device can't start up at maximum current if voltage on the gate isn't present first. We really need to know what the rest of the schematic is to be sure.

Brian.

 

[yefj]

Hello Brian, My input are 3 pins +12V -12V and GND.As I said the load is a TGA2227.
Could you say what input should I increase graually?
Could you say the logic of the different part so I could understand the inner workings logic?
Thanks.

TGA2227-SM - Qorvo

www.qorvo.com

"but if the voltage rises slowly, the outputs will switch in sequence. Try a simulation and slowly increase the input voltage to see how the outputs changes."

"This is often done in MOS amplifiers to ensure the gate voltage is present before the drain voltage or vice versa, depending on the design so the device can't start up at maximum current if voltage on the gate isn't present first."

 

[danadakk]

A simple way of doing a sequenced supply with a low end micro and block programming :

Pulse Sequence Generator / Smart Timer

Often users, developers, hobbyists need timed and qualified event generators, many resorting to 555 timers and the like. The venerable 555 has had a long run but its limited in accuracy and capability. This approach uses block language to create...

www.electro-tech-online.com

So for example say this is the startup sequence

switch turn on >> trigger supply 1 >> wait until V achieved >> trigger supply 2 >> wait 1 sec >> trigger supply 3........

So this approach can trigger a supply from a logic input/switch, a V, or delays, sequentially as desired
with various delays.

Delays, type of trigger trivial to program. You just have to add MOSFETs external to switch
the target supply or use a bigger package to get more I/O.

Using a ATTINY85 for a 6 (#triggers + #outputs) design

And it would be easy to add fault detection, like a supply drops out or does not come
hup in a specified period.


Regards, Dana.

--- Updated Aug 28, 2024 ---

A more sophisticated approach using a SOC for this problem. You want ability to measure V and I, and
apply a sequence of tests/tasks.

Here is a part (1 chip) with power control and fault capability (you must use external FETs for main power
switching) :