library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity tb_parity_generator is
end entity tb_parity_generator ;
architecture simulation_tb_parity_generator of parity_generator is
component parity_generator is
port
(
CLK : in std_logic ;
RST : in std_logic ;
INPUT : in std_logic_vector ( 1 downto 0 ) ;
OUTPUT : out std_logic
) ;
end component parity_generator ;
signal stimulus_clk : std_logic := '0' ;
signal stimulus_rst : std_logic ;
signal stimulus_input : std_logic_vector ( 1 downto 0 ) ; -- from file
signal stimulus_output : std_logic ; -- to file
begin
stimulus_rst <= '1' , '0' after 20 ns ;
stimulus_clk <= not stimulus_clk after 10 ns ;
reading_from_file : process ( CLK )
file my_file : text is in "input_stimulus.txt" ;
variable current_line : line ;
variable current_slv : std_logic_vector ( 1 downto 0 ) ;
begin
if ( not endfile ( my_file ) ) then
if rising_edge ( CLK ) then
readline ( my_file , current_line ) ;
read ( current_line , current_slv ) ;
end if ;
end if ;
stimulus_input := current_line ;
end process ;
simulation : parity_generator
port map
(
CLK => stimulus_clk ,
RST => stimulus_rst ,
INPUT => stimulus_input ,
OUTPUT => stimulus_output
) ;
end architecture simulation_tb_counter ;