VHDL file IO simulation

[shaiko]

Please note the "reading_from_file" process.
Is it any good?

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
		
entity tb_parity_generator is                                                                            	                                    
end entity tb_parity_generator ;

architecture simulation_tb_parity_generator of parity_generator is

component parity_generator is 
port					
( 		
  CLK : in std_logic ;
  RST : in std_logic ;
  INPUT : in std_logic_vector ( 1 downto 0 ) ;
  OUTPUT : out std_logic 
) ;	 	 				                                       
end component parity_generator ;

signal stimulus_clk : std_logic := '0' ;
signal stimulus_rst : std_logic ;
signal stimulus_input : std_logic_vector ( 1 downto 0 ) ; -- from file 
signal stimulus_output : std_logic ; -- to file

begin

stimulus_rst <= '1' , '0' after 20 ns ;
stimulus_clk <= not stimulus_clk after 10 ns ;
	
reading_from_file : process ( CLK ) 
file my_file : text is in "input_stimulus.txt" ; 
variable current_line : line ;
variable current_slv : std_logic_vector ( 1 downto 0 ) ;
begin
  if ( not endfile ( my_file ) ) then
    if rising_edge ( CLK ) then
      readline ( my_file , current_line ) ;
      read ( current_line , current_slv ) ;	
    end if ;
  end if ;	
  stimulus_input := current_line ;
end process ;		

simulation : parity_generator 
port map 
( 		
  CLK => stimulus_clk ,
  RST => stimulus_rst ,
  INPUT => stimulus_input ,
  OUTPUT => stimulus_output
) ;	 	 	
             	
end architecture simulation_tb_counter ;

 

[FvM]

Please note the "reading_from_file" process.
Is it any good?

Basically yes, I think.
The final assignment should be stimulus_input := current_slv;

Here's a process that I used to playback oscilloscope data for a signal processing simulation, in this case with decimal formatted data:

---

Code VHDL - [expand]
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Process
    file IN_DAT : text open read_mode is "scope.txt";
    variable LI: line;
    variable MV: integer;
    Begin
        while not (endfile(IN_DAT)) loop
                wait until rising_edge(clk);
                readline (IN_DAT, LI);
                read (LI, MV); 
                adc <= std_logic_vector(to_signed(MV,12)) XOR X"800";
        end loop;
        file_close(IN_DAT);
        wait;       
    End Process;

---

 

[TrickyDicky]

Apart from the syntax errors (it is much easier to syntax check with your compiler rather than a forum) and the old '87 file declarations, it will work.

'93 and beyold file syntax:
file my_file : text open read_mode is "some_text_file";

this allows you to open a file in read_mode, write_mode and append_mode. It also allows you declare a file:
file my_file : text;

and then open it in-line with FILE_OPEN and FILE_CLOSE procedures (built into the language). You cant do these with '87 syntax.

 

[shaiko]

it is much easier to syntax check with your compiler rather than a forum

And now that I have a compiler in front of me I can do just that.

This is the code (adjusted per your notes):

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use std.textio.all ;	

entity tb_parity_generator is                                                                            	                                    
end entity tb_parity_generator ;

architecture simulation_tb_parity_generator of parity_generator is

component parity_generator is 

port						
( 		
  CLK : in std_logic ;
  RST : in std_logic ;
  INPUT : in std_logic_vector ( 1 downto 0 ) ;
  OUTPUT : out std_logic 
) ;	 	 				                      
end component parity_generator ;

signal stimulus_clk : std_logic := '0' ;
signal stimulus_rst : std_logic ;
signal stimulus_input : std_logic_vector ( 1 downto 0 ) ; -- from file 
signal stimulus_output : std_logic ; -- to file 

begin

stimulus_rst <= '1' , '0' after 20 ns ;
stimulus_clk <= not stimulus_clk after 10 ns ;
	
process ( CLK ) is
file my_file : text open read_mode is "input_stimulus.txt" ; 
variable current_line : line ;
variable current_slv : std_logic_vector ( 1 downto 0 ) ;
begin
  if ( not endfile ( infile ) ) then
    if rising_edge ( CLK ) then
      readline ( my_file , current_line ) ;
      read ( current_line , current_slv ) ;	
    end if ;
  end if ;	
  stimulus_input := current_slv ;
end process ;	
	
simulation : parity_generator 
port map 
( 		
  CLK =>	stimulus_clk ,
  RST =>	stimulus_rst ,
  INPUT => stimulus_input ,
  OUTPUT => stimulus_output
) ;	 	 	
                                      	
end architecture simulation_tb_parity_generator ;

I get the following errors:

Unknown identifier "text".
FILE declaration must have a subtype indication that is a file type.
(vcom-1136) Unknown identifier "line".
(vcom-1136) Unknown identifier "endfile".
Type error resolving prefix expression "not" as type std.STANDARD.BOOLEAN.
(vcom-1136) Unknown identifier "readline".
Signal "stimulus_input" cannot be target of variable assignment statement.
Target type ieee.std_logic_1164.STD_LOGIC_VECTOR in variable assignment is different from expression type (error).

P.S: Modelsim is set to VHDL2008.

 

[TrickyDicky]

I dont know what code you're compiling - I get these errors, which are easy fixes. When you fix the first error:

architecture simulation_tb_parity_generator of parity_generator is

should be

architecture simulation_tb_parity_generator of tb_parity_generator is

You get these errors:

# ** Error: testcode.vhd(32): (vcom-1136) Unknown identifier "CLK".
# 
# ** Error: testcode.vhd(32): Expression is not a signal.
# ** Error: testcode.vhd(37): (vcom-1136) Unknown identifier "infile".
# 
# ** Error: testcode.vhd(37): Type error resolving prefix expression "not" as type std.STANDARD.BOOLEAN.
# ** Error: testcode.vhd(38): (vcom-1136) Unknown identifier "CLK".
# 
# ** Error: testcode.vhd(43): Signal "stimulus_input" cannot be target of variable assignment statement.
# ** Error: testcode.vhd(55): VHDL Compiler exiting

 

[shaiko]

oops, didn't catch that.
Code compiles - waveform presented.
Thanks a lot for your help and sorry for the slow torture.

I'll keep this post alive for issues I encounter while reading from files.
I'll start another post for writing to files when I get there...

Please stay posted,
Thanks again.