library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity parity_generator is
port
(
CLK : in std_logic ;
RST : in std_logic ;
INPUT : in std_logic_vector ( 1 downto 0 ) ;
OUTPUT : out std_logic
) ;
end entity parity_generator ;
architecture synthesizable_parity_generator of parity_generator is
begin
process ( CLK , RST ) is
begin
if RST = '1' then
OUTPUT <= 'Z' ;
elsif rising_edge ( CLK ) then
OUTPUT <= INPUT ( 0 ) xor INPUT ( 1 ) ;
end if ;
end process ;
end architecture synthesizable_parity_generator ;
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The syntax...What exactly are you having trouble with?
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Yes. I did. It raised more questions then it answered.Did you review the available textio procedures?
OK...Why not just try and we can comment on what you did?
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity tb_parity_generator is
end entity tb_parity_generator ;
architecture simulation_tb_parity_generator of parity_generator is
component parity_generator is
port
(
CLK : in std_logic ;
RST : in std_logic ;
INPUT : in std_logic_vector ( 1 downto 0 ) ;
OUTPUT : out std_logic
) ;
end component parity_generator ;
signal stimulus_clk : std_logic := '0' ;
signal stimulus_rst : std_logic ;
signal stimulus_input : std_logic_vector ( 1 downto 0 ) ; -- from file
signal stimulus_output : std_logic ; -- to file
begin
stimulus_rst <= '1' , '0' after 20 ns ;
stimulus_clk <= not stimulus_clk after 10 ns ;
simulation : parity_generator
port map
(
CLK => stimulus_clk ,
RST => stimulus_rst ,
INPUT => stimulus_input ,
OUTPUT => stimulus_output
) ;
end architecture simulation_tb_counter ;
OK...
This is my basic TB.
Code:library ieee ; use ieee.std_logic_1164.all ; use ieee.numeric_std.all ; entity tb_parity_generator is end entity tb_parity_generator ; architecture simulation_tb_parity_generator of parity_generator is component parity_generator is port ( CLK : in std_logic ; RST : in std_logic ; INPUT : in std_logic_vector ( 1 downto 0 ) ; OUTPUT : out std_logic ) ; end component parity_generator ; signal stimulus_clk : std_logic := '0' ; signal stimulus_rst : std_logic ; signal stimulus_input : std_logic_vector ( 1 downto 0 ) ; -- from file signal stimulus_output : std_logic ; -- to file begin stimulus_rst <= '1' , '0' after 20 ns ; stimulus_clk <= not stimulus_clk after 10 ns ; simulation : parity_generator port map ( CLK => stimulus_clk , RST => stimulus_rst , INPUT => stimulus_input , OUTPUT => stimulus_output ) ; end architecture simulation_tb_counter ;
Should I add both IEEE.STD_LOGIC_TEXTIO and STD.TEXTIO ?
What does each one do?
Of topic question,All file extensions are legal. The file extension is meaningless - its just a name. The file must be a text file though.
I didn't say it should be part of the VHDL spec. It was a general question...I don't see how processing of unformatted binary files should be specified in VHDL.
I see that the type definition complies with general VHDL syntax rules. But I didn't expect that Modelsim would support it. Good to know.There are ways you can read binary files in VHDL. In modelsim you can use:
file data_f_t is file of character
and that gives you byte access.
I see that the type definition complies with general VHDL syntax rules. But I didn't expect that Modelsim would support it.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 function char_to_slv( c : character ) return std_logic_vector is begin return std_logic_vector(to_unsigned(character'pos(c), 8)); end function char_to_slv; procedure read_bytes( file f : data_file_t; variable s : out std_logic_vector ) is variable c_buf : character; begin for i in 0 to (s'length/8) -1 loop read(f, c_buf); s( (8*i) +7 downto i*8 ) := char_to_slv(c_buf); end loop; end procedure read_bytes;
The numbers are characters - how do I convert them to std_logic_vectors ?00
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readln(f,l);
read(l,my_slv2);
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