VFC design revisiting

[curious_mind]

Trying to model a VFC, circuit shown below. Idea is that output Vcomp will switch the mux to negative reference to discharge from capacitor. Typically trying to emulate charge balance type VFC. I am unable to get any output. What could be wrong? Is this approach correct?
Logic zero in Vdig connects 10V from mux and Logic one in Vdig connects -10V to the summing point.

btw: if the vref 10V and -10V is greater than input, then I do see some oscillations.

 

[FvM]

Wrong comparator logic. You can either use a single comparator with hysteresis or two comparators with a RS latch (cross coupled NAND or NOR gates)

 

[curious_mind]

Hi FVM,

See the figure. It does not work. Only pulse width is getting adjusted and not the frequency

 

[FvM]

O.k, I was only focussing on making the circuit oscillate, not on the VFC function. VFC needs a single comparator and a monoflop.

 

[curious_mind]

please suggest the modifications in the circuit

 

[danadakk]

Do you have some basic goals, like range of F and V, linearity, step response....

Is this specific approach the only VFC architecture you will consider ? Preferred
output waveform, square, rectangular, tri, sine.....?


Regards, Dana.

 

[curious_mind]

I am just trying to just model the architecture of charge balance VFC. Need help w.r.t to getting accurate model. My crude specs are 0-100KHz square wave with 0.1% linearity at output. You may suggest any architecture that works for this specifications

 

[KlausST]

Hi,

When I do an internet search on "v-f-converter circuit" there come up many schematics.
So there you may get ideas as well as proven circuits. No need to design from scratch.

Also there are ready to buy VFC ICs.
* You may use them as they are
* you may use the given informations to build your own
* you may use their application notes as they include more detailed informations on design, calculations... how to get good linearity

Btw: 0.1%linearity on 0..100kHz. How do you define the error at 0 Hz in %.
It is not possible unless you refer the error just on the 100kHz, which then is 100Hz for the whole range.
For good linearity good capacitors are urgent. Maybe try wired PS film capacitors.

Klaus

 

[danadakk]

Voltage to Frequency Converters | Analog Devices

Analog Devices has the widest range of voltage-to-frequency converters (VFCs) for the instrumentation, industrial, and automation markets. They are ideally suited for use in analog-to-digital conversion, long-term integration, linear frequency modulation and demodulation, and...

www.analog.com

**broken link removed**

https://www.analog.com/media/en/technical-documentation/application-notes/an14f.pdf

Maybe above can help.


Regards, Dana.

 

[curious_mind]

Finally I got the schematics from https://www.multisim.com/content/6L...amp-comparator-voltage-controlled-oscillator/. Tried in TINA-TI and it works. Can somebody explain, how this circuit behaves. In particular, not very clear why R4, R8 and R2 have to be half of R1. Only then the circuit oscillates. Secondly inverting integrator produces negative output (U2), then how does it work with single supply voltage? Role of R4 and R8?. I understand that U1 is schmitt trigger

 

[FvM]

I don't fully understand the question. You see it working in simulator, thus you can observe the behaviour of each node voltage.

inverting integrator produces negative output (U2)

Nope. It can produce negative output, but the used output range is set by the ST thresholds, which are both positive.

The first stage is a combination of amplifier with switchable gain sign and an integrator. Oscillation can only occur if the gain sign is actually switched, the condition is set by resistor ratios.

For clarity, you might implement the switchable gain inversion and integrator as separate stages.

 

[curious_mind]

[You see it working in simulator, thus you can observe the behavior of each node voltage]
.

yes, but I wanted to understand why it behaves this way. Rationality for putting those resistors in non-inverting input

 

[FvM]

amplifier with switchable gain sign

-> positive gain with closed switch, negative gain with open switch.

 

[d123]

Hi,

R4 and R8 bias IN+ to V1/2. Not sure why that bias/reference is needed.

 

[FvM]

See e.g. switchable G=+/-1 stage

--- Updated Oct 31, 2020 ---

V1 is variable input signal, not bias.

 

[curious_mind]

Hi FvM

Sorry I did not get it. The central idea is to create a triangle wave.( I can see that in simulation). This would happen if we charge and discharge equally. Now i could not understand the relation between gain switching and triangle wave generation.

 

[FvM]

To generate a triangle wave, the input signal has to be fed to the integrator with alternating polarity. For equal rise and fall slope, the current into C1 must have equal magnitude in both phases. You can calculate that this is the case for the given resistor ratios.

 

[curious_mind]

Revisiting the thread

I replaced mosfet with ADG1201 switch. Tried this time in LTSPICE. The output seems to be not working. Why? Files are provided.

 

[FvM]

ADG1201 symbol and subcircuit are missing in your archive. With ADG1201 model included in most recent LTspice version, the circuit works. Thus I guess you have wrongly connected subcircuit.

 

[KlausST]

Hi,

"does not work" means what?
TRy to use standard symbols instead of "package style" symbols. It makes it difficult to read which pin is which. We nned to search for the datasheet and then there additionally is theis odd pin numbering...

V4 is rather useless. Try your simulation wiht V4 disconnected to see the (slight) difference.

Klaus