VerilogA model of monostable block

veriloga absdelay

Hi, guys,

I want to write a model using VerilogA for a monostable. But I cannot find the suitable delay statement for the pulse width of the monostable.

Can somebody help me?

Thanks a lot.

B. F.

vhdl monostable

why don't you just describe the circuit in terms of transistors and capacitors. A couple of level 1 equations and ohms law, should be easy enough to lash together.

I've never programmed in verilogA, but I used to do a fair bit with VHDL AMS, and it would be relatively simple to do that in VHDL and I assume that verilogA is at least as easy.

**broken link removed**

There's a monostable circuit in the above link. It shouldn't be hard to code that. Just make a model for a resistor, a capacitor, etc and link them together.

verilog-a $display

Thank you Nick,

Yes. I can use circuit to implement the monostable. But I want the simulation speed to be faster. That's why I want to use VerilogA.

monostable verilog

jwfan said:

Thank you Nick,

Yes. I can use circuit to implement the monostable. But I want the simulation speed to be faster. That's why I want to use VerilogA.

Click to expand...

If you use R=V/I and low level equations, then the time taken to simulate that will be minimal, maybe 30 clock cycles per time step.

will you not be able to use the
'timescale attribute to define a timescale with the # to define the time?

monostable in verilog-a

I find the absdelay statement.

The VerilogA program is list below, in case someone may need it. Thanks,

// VerilogA for PMM_VA_Models, mono, veriloga

`include "constants.vams"
`include "disciplines.vams"

module mono(vin, vout);
electrical vin, vout, vindelay;
parameter real vlogic_high = 5;
parameter real vlogic_low = 0;
parameter real vtrans = 1.4;
parameter real tdel = 2u;
parameter real pulsew = 3u;
parameter real trise = 1u;
parameter real tfall = 1u;


real vout_val;
integer logic1;

analog begin

@ ( initial_step ) begin
if (vlogic_high < vlogic_low) begin
$display("Range specification error. vlogic_high = (%E) less than vlogic_low = (%E).\n", vlogic_high, vlogic_low );
$finish;
end
if (vtrans > vlogic_high || vtrans < vlogic_low) begin
$display("Inconsistent $threshold specification w/logic family.\n");
end
end

@(initial_step)logic1 = 0;

V(vindelay) <+ absdelay(V(vin), pulsew);


@ (cross(V(vin) - vtrans, 1)) logic1 = 1;
@ (cross(V(vindelay) - vtrans, 1)) logic1 = 0;


vout_val = (logic1) ? vlogic_high : vlogic_low;
V(vout) <+ transition( vout_val, tdel, trise, tfall);

end

endmodule

Hi,

can anyone tell about "vtrans" used in verilogA code?
Thanks