ESD device model library by foundry

[Mason_Yang]

I'm an ESD engineer and I'm wondering if TSMC offers an ESD device SPICE model library.
As far as I know, legacy processes don't provide them.
Does anyone have experience with recent TSMC process nodes including ESD device SPICE models for simulation with other analog circuits?
Any information on specific process nodes would be greatly appreciated, but even a simple "yes" or "no" would be helpful.

 

[dick_freebird]

Sometimes I see ESD libraries and sometimes I don't, not a
TSMC user. If you want information for -a- specific process
then you need to say which (and more than a yes/no, probably
need to go to the foundry as every customer is NDA'd up.

If there is no ESD library then ESD protection is made with
standard elements (well laid out and properly modeled, you
hope). Then you care about geometry and rules, if you mean
to simulate ESD protection or design it. Which would be
instance-specific and probably customer proprietary.

I've always preferred to design from scratch, having little trust
in modeling for abnormal applications. One place I worked
had ESD clamp devices in the kit but the model had nothing
for emulating breakdown electrical response, which besides
leakage is the only care-about - I had to fit my own and pass
around to other designers, under the table. The CAD b!tches
wouldn't even take my fitted subcircuit under support. And as
nobody (but me) ever even pulled pulsed stress curves, or
did any failure analysis of ESD test samples after go/no-go,
nobody ever noticed that the features placed to "improve"
ESD clamp leakage, were -exactly- where -every- ESD fail
hotspot was found.

Trust noone.

 

[BigBoss]

ESD Devices will not be functional under normal operating conditions. Their performances are just measured not simulated.
So, you don't need a model for them. Some important parameters are given (capacitances, breakdown voltages etc.) otherwise models of a ESD device is useless.

 

[dick_freebird]

I like having valid (incl abnormal conditions) models
so I can -design- protection per pin.

A basic MOSFET model for a GGNMOS clamp has
little use because MOS models don't do breakdown.
You have to macromodel it. But after doing the work
(models & methods) we started meeting part ESD
goals.

I built my own TLP, pulled the pulsed overstress
response (I and V) and fitted a hokey diode
avalanche model BV & RS, let the MOSFET carry
the C as it was already fitted to do, and there you go.

Some designers get to "let sleeping dogs lie". I get
to dance with wolves.

 

[Mason_Yang]

Thank you for all the replies!!

I also create MPWs to measure the TLP curve of ESD devices when necessary, and I sometimes model them simply with a macro model or an ideal diode.
In the past, when I used Samsung Foundry, there were cases where the ESD engineers would create models for me if I requested them.
Recently, I've been using TSMC's process, but it's been difficult to communicate with the ESD engineers, and I can't even find out if there are models available or not. That's why I'm asking if anyone else has experience with this.
For the two processes I've used (180nm and 12nm), ESD models were not provided. I'm wondering if this is because they are legacy processes.
I'm also curious if models are provided for the latest processes such as 3nm and 4nm.
If they are not provided, I guess I have no choice but to create them myself using MPW.

 

[dick_freebird]

For mature TSMC flows it looks like there's some third
party ESD IP to be had, though in skimming some not-
so-mature-looking details (like needing waivers) can be
seen. If you mean to lay out your own this sarch phrase
turns up some design-and-results type papers too

tsmc esd 180