bigdogguru
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Please post your recommendations or critiques of books concerning Verilog HDL.
I have read several books dealing with Verilog over the past eight months, the following are two which I can strongly recommend:
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Verilog HDL (2nd Edition) by Samir Palnitkar
A very good book for the beginner to intermediate user of Verilog. Assumes little or no previous knowledge of HDLs and builds a solid understanding of Verilog's syntax and operation. The book is also an excellent guide to writing testbenches, which most other texts seem to lack. It does however concentrate on simulation and deals with very little on synthesis and its related problems and issues.
**broken link removed**
FPGA Prototyping By Verilog Examples: Xilinx Spartan-3 Version by Pong P. Chu
An excellent introduction into synthesis using the Verilog HDL. Chu concentrates on the synthesizable subset of Verilog and using Xilinx's ISE and Digilent development board effectively demonstrates the problems and issues concerning the synthesis of a design in Verilog. The text also covers testbenches and their necessity to the design path.
I'm eager to read some of your recommendations.
I have read several books dealing with Verilog over the past eight months, the following are two which I can strongly recommend:
**broken link removed**
Verilog HDL (2nd Edition) by Samir Palnitkar
A very good book for the beginner to intermediate user of Verilog. Assumes little or no previous knowledge of HDLs and builds a solid understanding of Verilog's syntax and operation. The book is also an excellent guide to writing testbenches, which most other texts seem to lack. It does however concentrate on simulation and deals with very little on synthesis and its related problems and issues.
**broken link removed**
FPGA Prototyping By Verilog Examples: Xilinx Spartan-3 Version by Pong P. Chu
An excellent introduction into synthesis using the Verilog HDL. Chu concentrates on the synthesizable subset of Verilog and using Xilinx's ISE and Digilent development board effectively demonstrates the problems and issues concerning the synthesis of a design in Verilog. The text also covers testbenches and their necessity to the design path.
I'm eager to read some of your recommendations.