Verilog HDL AES 128 bits ENCRYPTION DECRYPTION

[Kaival_2934]

I am currently working on a project "AES 128 bits ENCRYPTION DECRYPTION", using Verilog HDL.
Now the problem I am facing is that while simulation- if i provide a plain text all zeros, it gets decrypted perfectly. But when i provide a big number like all ones in plain text, the decryption doesnt work perfectly i.e. i dont get the original plaintext. I tried with various plaintexts like for some i get the decryption perfect but for some i dont get the accurate decryption output.
I also cross-checked my logic, it is correct...
Can you please help me with this? What can be the solution for this problem?

 

[dpaul]

Let open my magic crystal ball.....if it can show me what someone else has done!

PS - you have not provided enough info even for someone else to guess the problem!
I recommend you to read this first - https://princetonuniversity.github....l-questions/HowToAskQuestions2018Bootcamp.pdf

 

[sky_siliconthink]

First, you need a algorithm model to verify the function of verilog code.
So, you can find some c model from github, e.g. https://github.com/kokke/tiny-AES-c
You may even find some RTL implementation on github.

BTW, the episode talks about the basic verilog simulation enviroment:

I am currently working on a project "AES 128 bits ENCRYPTION DECRYPTION", using Verilog HDL.
Now the problem I am facing is that while simulation- if i provide a plain text all zeros, it gets decrypted perfectly. But when i provide a big number like all ones in plain text, the decryption doesnt work perfectly i.e. i dont get the original plaintext. I tried with various plaintexts like for some i get the decryption perfect but for some i dont get the accurate decryption output.
I also cross-checked my logic, it is correct...
Can you please help me with this? What can be the solution for this problem?