pakha
Newbie level 4
Hi,
Design a two stage pipeline 16 bits adder with verilog code, assume you can use
the 8 bit adder macro module .The input and output signals are defined as:
input [15:0] a, b;
input clk, cin, rst;
(rst is asynchronous reset signal, only reset at neg
ative edge)
output [16:0] sum;
output: cout
Can anyone provide me the verilog code for this. Please it's very urgent
Design a two stage pipeline 16 bits adder with verilog code, assume you can use
the 8 bit adder macro module .The input and output signals are defined as:
input [15:0] a, b;
input clk, cin, rst;
(rst is asynchronous reset signal, only reset at neg
ative edge)
output [16:0] sum;
output: cout
Can anyone provide me the verilog code for this. Please it's very urgent