Verilog code for BCD to Floating point representation

[KlausST]

Hi,

What´s the problem with "updating your own drawing" with the requested informations?

I will come back if I see that you - at least try to - do what you have been toold.

Klaus

 

[c_mitra]

The scaling and display has to be done in software.

I am not going to write the code for you but I shall show the way.

Let us assume that the ADC max scaling is set at 3.3V. I assume that your ADC is configured at 12bits, single ended (unsigned).

In that case 3.3V ---> 2^12-1 (4095)

any arbitrary voltage between 0-4095 will be scaled linearly ---> x*3.3/4096 (this will be a float value)

But you will have to compute this in integer mode; so need some tricks.

Fix the decimal point at the 2nd position from the left (X.ABC)- your display will tell how to do that.

Now scale the result by 1000; you will get x*3300/4096 (dividing by 4096 in binary is not difficult)

Hence multiply x*3300 (the result must be long int)- shift the result 12 bit to get the final result (with a factor of 1000)

Put the result in 16 bits. This is the required result. You will have to split in four digits.

Let the result, call that res. digit1 (rightmost) = remainder (res/10); res1=quotient(res/10)

digit2=remainder(res1/10); res2=quotient(res1/10)

digit3=remainder(res2/10); res3=quotient(res2/10)

digit4=remainder(res3/10); res4=quotient(res3/10)

res4 should be zero; test for it!!

Send digit1, digit2, digit3 and digit4 to the display (low 4bits; as needed; high 4bits should be zero)

Test with some random value for x (0-3.3)- just to convince yourself.

 

[FvM]

First part of your answer (ADC result scaling to integer millivolt) has been already discussed in post #6 and #7.

BCD conversion with /10 division isn't particularly effective in FPGA, that's why post #6 suggests double dabble algorithm.

 

[niciki]

any arbitrary voltage between 0-4095 will be scaled linearly ---> x*3.3/4096 (this will be a float value)
...
Now scale the result by 1000; you will get x*3300/4096

I am sure this is obvious, but I would like to point that if we want to be precisely, it should be x*max_analog/max_digital. That is x*3.3/4095
but we use FPGA, so it is the best if we would divide by the power of 2 (then we use shifting instead of division). That is if we approximate the value 4095 to its near power of 2 value, which is 2^12 = 4096, we get the above equation: x*3.3/4096

 

[FvM]

if we want to be precisely, it should be x*max_analog/max_digital. That is x*3.3/4095
but we use FPGA, so it is the best if we would divide by the power of 2 (then we use shifting instead of division). That is if we approximate the value 4095 to its near power of 2 value, which is 2^12 = 4096, we get the above equation: x*3.3/4096

Although the OP requested a factor of 1/4095, it's not necessarily the exact solution. Most 12-bit ADC have a quantization step of Vref/4096. If you want a non-power-of-denominator though, you'll recalculate the numerator respectively.

 

[KlausST]

Hi,

Most 12-bit ADC have a quantization step of Vref/4096

True, indeed I don't know a single ADC or DAC that uses 4095 (or 1023)
They all use digital_value = analog_value × 2^n / VRef.

Since the digital value is 0...4095, the most highest voltage it can represent is VRef × 4095 / 4096.

In detail one needs to consult the datasheet.

Klaus

 

[c_mitra]

I would like to point that if we want to be precisely, it should be x*max_analog/max_digital. That is x*3.3/4095...

Obviously this will be an error term and will be consumed by the +/-1 LSB accuracy of the ADC. But more than that, you will need a 6 or 7 digit display to make out any difference.

In reality, you may find the last digit fluctuating and practically unreadable. In fact, ADC results 1-2-3 will just appear as zero in the display...

 

[adhul]

Hi,

What´s the problem with "updating your own drawing" with the requested informations?

I will come back if I see that you - at least try to - do what you have been toold.

Klaus

Updated diagram

 

[FvM]

Regarding the text in "updated diagram", seems like you are repeating questions that have been already answered throughout this thread.

 

[niciki]

We really want to help you, but you don't step forward and don't cooperate.

My last attempt to help you: how FPGA is connected with a 7segs?
Please attach the drawings.

 

[vGoodtimes]

I think I would just use a small FSM with maybe a 32b accumulator, a 4b counter, and a binary to bcd circuit.

1V = 1241.21 repeating counts. adding 20 bits of fractional precision gives:
1V = 1301505242 (must round up if not exactly an integer).
100mV = 130150525.
10mV = 13015053.
1mV = 1301505 (can round normally.)

From there you have a FSM that loads the 32b accumulator with the 12b sample in the 12msb and 0's for the lower 20 bits. each cycle where the accumulator is greater than the accumulator for 1V, subtract that value and add 1 to the counter. When the accumulator is less than the 1V value, the counter has the 1's place for voltage. The counter is then reset. Then the fsm does the same thing with the 100mV value. This is why the 100mV value was rounded up -- it had to avoid ever getting a value of "10". The process repeats for the 10mV and then the 1mV case. It takes around 2 + 9 + 9 + 9 = 29 cycles to convert the value in the worst case. a little longer if the fsm has extra states. (32b is also much larger than needed, but is fine for modern devices).

 

[c_mitra]

Updated diagram...

What is the nature of the display? Does it come with integrated drivers? Most of the 7-seg displays has a decimal and you need not waste one display to show the decimal.

Each bcd will need 4 data lines and 4 digits will take 16 data connections. But most come will multiplex facility. In that case, 4 data lines and 4 display select lines (total 8; not counting the ground).

The driver may have the brightness (current control) but that can be seen later.

 

[FvM]

A Verilog implementation of double dabble algorithm can be e.g. found here (didn't check the code) https://www.nandland.com/vhdl/modules/double-dabble.html