Variable length Correlation in VHDL

[azwaa]

Okey ;


Thank you ;

 

[FvM]

use IEEE.math_real.all;

use IEEE.math_real."ceil";
use IEEE.math_real."log2";

1. ceil and log2 are part of math_real. The first line should already include it. In case of doubt review the library definition of your VHDL tool.
2. the additional lines have wrong syntax

 

[azwaa]

For the easy option, you need to just make everything the output length from the beginning.

something like this:

---

Code VHDL - [expand]
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type mult_array_t is array(0 to longueur-1) of signed(15 downto 0);
type adder_stage_t is array(0 to longueur/2-1) of signed(Q'length-1 downto 0);
 
type adder_tree_t is array(0 to log2(longueur)-1) of adder_stage_t;
 
signal mults : mult_array_t;
signal adders : adder_tree_t;
 
...
--multiplies:
 
mult_proc : process(clk)
begin
  if rising_edge(clk) then
    for i in mults'range loop
      mults(i) <= ip(i) * C(i);
    end loop;
    
    --initial adders:
    for i in adders(0)'range loop
      adders(0)(i) <= resize(mults(i*2), Q'length) + resize( mults(i*2 +1), Q'length);
    end loop;
    
    --other adder stages:
    for level in 1 to adders'high loop
      for i in 0 to longueur/ (2**(level+1)) loop
        adders(level)(i) <= adders(level-1)(i*2) + adders(level-1)(i*2 + 1);
      end loop
    end loop;
  end if;
end process;
 
Q <= adders(adders'high)(0);

---

- - - Updated - - -

Doing this, the synthesisor can trim any unused bits.

Thank you

- - - Updated - - -

use IEEE.math_real.all;

use IEEE.math_real."ceil";
use IEEE.math_real."log2";

1. ceil and log2 are part of math_real. The first line should already include it. In case of doubt review the library definition of your VHDL tool.
2. the additional lines have wrong syntax

Thank you

 

[azwaa]

For the easy option, you need to just make everything the output length from the beginning.

something like this:

---

Code VHDL - [expand]
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type mult_array_t is array(0 to longueur-1) of signed(15 downto 0);
type adder_stage_t is array(0 to longueur/2-1) of signed(Q'length-1 downto 0);
 
type adder_tree_t is array(0 to log2(longueur)-1) of adder_stage_t;
 
signal mults : mult_array_t;
signal adders : adder_tree_t;
 
...
--multiplies:
 
mult_proc : process(clk)
begin
  if rising_edge(clk) then
    for i in mults'range loop
      mults(i) <= ip(i) * C(i);
    end loop;
    
    --initial adders:
    for i in adders(0)'range loop
      adders(0)(i) <= resize(mults(i*2), Q'length) + resize( mults(i*2 +1), Q'length);
    end loop;
    
    --other adder stages:
    for level in 1 to adders'high loop
      for i in 0 to longueur/ (2**(level+1)) loop
        adders(level)(i) <= adders(level-1)(i*2) + adders(level-1)(i*2 + 1);
      end loop
    end loop;
  end if;
end process;
 
Q <= adders(adders'high)(0);

---

- - - Updated - - -

Doing this, the synthesisor can trim any unused bits.

Thank you My friends