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Using $fsdbDumVars() system task. This is from Novas, see: www.novas.com, a google search for fsdbdumpvars will give you lot of details if needed.
BTW, nowadays the built-in debuggers are quite powerful (Such as Simvision, Modelsim, DVE-VCS) and hence unless you have a strong need Novas is not really needed.
Hi,
I have been using GTKwave for quite some time. Verilog allows me to design modules and primitives with a finite rise/fall time. But while viewing the waveforms in GTKwave, all the edges are vertical. Its a little counterintuitive to work with such waveforms.
Is there a solution for this? How can i get a sloping edge transition? Is it possible to view a realistic rising edge with VCD files??
Happy to have a nice discussion regarding the VCD file.
I tried to generate a VCD file using $dumpvars and the filename i used is "dump1.vcd" but nothing is written in the VCD file.
Once when i change the dumpfile name to "dump2.vcd then am getting the result in the "dump1.vcd" file. why is it so.
I tried this four to five times and getting the same result.
dumpvars only selects which signals to be dumped. You might need to use dumpon and dumpoff to start/stop the dumping. Sometime the VCD file is empty while simulation runs as the VCD file buffer has not been flushed. if you stop and exit the simulation the file should be flushed.
This is just a guess .. at first case u can not dump any thing in dump1.vcd but can do only at second time wen u give it as dump2.vcd.
If I understnd u correctly the mistake ur doing is creating a new file of .vcd after u had given the commnad dumping the simulation signals .. so try to give the command of .vcd file as the first command in the mentor script and try again .
This code must be added to each Verilog testbench in order for a VCD file to be generated.
// The following code will generate a VCD file containing
// all of the nets in the instance t.uut. "t" is the module name of the
// testfixture, "uut" is the instance name
// of the design being tested.
initial begin
$dumpfile("invchn26.vcd"); // Change filename as appropriate.
$dumpvars(1, t.uut);
end
---------- Post added at 13:44 ---------- Previous post was at 13:43 ----------
For VHDL simulations, the commands to generate a VCD file must be entered interactively, or contained in a do file.
vcd file my_design.vcd
vcd add testbench/uut/*
This technique will work for both VHDL and Verilog in ModelSim.
Note: When creating a VCD file using the NC simulator, the command must include the -f switch.
The above lines generate a VCD file called my_design.vcd. The entity name of our testbench is testbench and the instance name of the unit under test is uut.
Using the -r switch with ModelSim's vcd add command, or specifying a number of levels other than 1 to the $dumpvars Verilog task will result in a large but significantly more accurate VCD file. Using the -r switch is highly recommended.
VCD files can grow quite large for larger designs, or even for smaller designs if the simulation run time is long enough. Using a VCD file to set the activity rates of signals in XPower may not be an efficient method for certain types of designs, e.g. watchdog timers.
XPower will only read a VCD file up until the first break in the simulation, or vcd off command. After this a warning message will be issued and all data following the vcd off or $dumpoff command in the VCD file will be ignored.
For more information on generating a VCD file from ModelSim, see section 9 of the ModelSim Xilinx User's Manual.
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