Using VHDL ring oscillator for FPGA

	logic_chain : for i in 1 to chain_width 
	generate
		chain ( i ) <= chain ( i - 1 ) ;
	end generate;
	chain ( 0 ) <= not chain ( 0 ) or RESET_I ;		

	
	

	t_flip_flop : process ( RESET_I , chain ( 0 ) )
	begin
		if RESET_I = '0' then
			RING_OSCILLATOR_GENERATED_CLOCK_O <= '0' ;
		elsif rising_edge ( chain ( 0 ) ) then
			RING_OSCILLATOR_GENERATED_CLOCK_O <= not RING_OSCILLATOR_GENERATED_CLOCK_O ; 
		end if ;	
	end process t_flip_flop ;

library ieee ;
	use ieee.std_logic_1164.all ;
	use ieee.numeric_std.all ;

		

		
entity ring_oscillator is                                                                                 

	generic
	( 
		chain_width : natural range 1 to 1000 := 50 -- must be an even number
	) ;                                        
																						
	port
	( 
		RESET_I : in std_logic ;
		RING_OSCILLATOR_GENERATED_CLOCK_O : buffer std_logic 
	) ;	                                        
	                                                                                       
end entity ring_oscillator ;




architecture synthesizable_ring_oscillator of ring_oscillator is	   

	signal chain : unsigned ( chain_width downto 0 ) ;
	
	attribute syn_keep: boolean;
	attribute syn_keep of chain : signal is true;
	


		  
begin

	logic_chain : for i in 1 to chain_width 
	generate
		chain ( i ) <= chain ( i - 1 ) ;
	end generate;
	chain ( 0 ) <= not chain ( chain_width ) or ( not RESET_I ) ;		

	
	

	t_flip_flop : process ( RESET_I , chain ( 0 ) )
	begin
		if RESET_I = '0' then
			RING_OSCILLATOR_GENERATED_CLOCK_O <= '0' ;
		elsif rising_edge ( chain ( 0 ) ) then
			RING_OSCILLATOR_GENERATED_CLOCK_O <= not RING_OSCILLATOR_GENERATED_CLOCK_O ; 
		end if ;	
	end process t_flip_flop ;	




end architecture synthesizable_ring_oscillator ;