Using VHDL ring oscillator for FPGA

[mrflibble]

Re: VHDL ring oscillator

Yep. And you want a bit of an asymmetrical setup as FvM already pointed out. I get okay results with half the chain at one part of the die, and the other half of the chain at another part of the die. You can use your favorite placements contraints for that.

 

[shaiko]

Re: VHDL ring oscillator

looks right ?

	logic_chain : for i in 1 to chain_width 
	generate
		chain ( i ) <= chain ( i - 1 ) ;
	end generate;
	chain ( 0 ) <= not chain ( 0 ) or RESET_I ;		

	
	

	t_flip_flop : process ( RESET_I , chain ( 0 ) )
	begin
		if RESET_I = '0' then
			RING_OSCILLATOR_GENERATED_CLOCK_O <= '0' ;
		elsif rising_edge ( chain ( 0 ) ) then
			RING_OSCILLATOR_GENERATED_CLOCK_O <= not RING_OSCILLATOR_GENERATED_CLOCK_O ; 
		end if ;	
	end process t_flip_flop ;

 

[K-J]

Re: VHDL ring oscillator

looks right ?

	logic_chain : for i in 1 to chain_width 
	generate
		chain ( i ) <= chain ( i - 1 ) ;
	end generate;
	chain ( 0 ) <= not chain ( 0 ) or RESET_I ;

Almost...should be
chain ( 0 ) <= not chain ( chain_width ) or RESET_I ;

Kevin Jennings

 

[shaiko]

Re: VHDL ring oscillator

that's assuming RESET_I is active low - am I correct ?

 

[FvM]

Re: VHDL ring oscillator

that's assuming RESET_I is active low - am I correct ?

No "or" refers to active high - a "1" overrides the loop feedback.

 

[shaiko]

Re: VHDL ring oscillator

for an active low reset with a stabilizing t flip flop the code should look like this ?

library ieee ;
	use ieee.std_logic_1164.all ;
	use ieee.numeric_std.all ;

		

		
entity ring_oscillator is                                                                                 

	generic
	( 
		chain_width : natural range 1 to 1000 := 50 -- must be an even number
	) ;                                        
																						
	port
	( 
		RESET_I : in std_logic ;
		RING_OSCILLATOR_GENERATED_CLOCK_O : buffer std_logic 
	) ;	                                        
	                                                                                       
end entity ring_oscillator ;




architecture synthesizable_ring_oscillator of ring_oscillator is	   

	signal chain : unsigned ( chain_width downto 0 ) ;
	
	attribute syn_keep: boolean;
	attribute syn_keep of chain : signal is true;
	


		  
begin

	logic_chain : for i in 1 to chain_width 
	generate
		chain ( i ) <= chain ( i - 1 ) ;
	end generate;
	chain ( 0 ) <= not chain ( chain_width ) or ( not RESET_I ) ;		

	
	

	t_flip_flop : process ( RESET_I , chain ( 0 ) )
	begin
		if RESET_I = '0' then
			RING_OSCILLATOR_GENERATED_CLOCK_O <= '0' ;
		elsif rising_edge ( chain ( 0 ) ) then
			RING_OSCILLATOR_GENERATED_CLOCK_O <= not RING_OSCILLATOR_GENERATED_CLOCK_O ; 
		end if ;	
	end process t_flip_flop ;	




end architecture synthesizable_ring_oscillator ;