UPF: power pin connection problems

[vince_g]

Error: The power pin VDD on the cell u_top/u_test/u_and2 is unconnected. (UPF-581)
-----------------------------------------------------------------------------------------------
Cell Power Pin Type Maximum Minimum Connected Power
Name Voltage Voltage Net
-----------------------------------------------------------------------------------------------
u_top/u_test/u_and2
VDD Primary Power 0.81 0.81 VDD (*)
u_top/u_test/u_and2
VSS Primary Ground 0.00 0.00 VSS (*)
-----------------------------------------------------------------------------------------------

Anyone has any idea how to solve this error? When I report_power_pin_info for the cell, it seems like my upf is read in and the power pins are connected to the supply nets but somehow when I ran check_mv_design the power pins are still unconnected.

 

[ThisIsNotSam]

you have to provide more details, context. what tool are you using? what is this cell you are trying to connect? is it a std cell or a custom cell or a power switch?

 

[vince_g]

Hi, currently running on DC compiler and it's a std cell. On RTL, I've let the port unconnected and was planning to do the power pin connection via UPF. Its so weird that it reports that it's connected but when I'm trying to compile the design it reports that it's still unconnected.

I've also tried to create a power domain wrapping the leaf std cells with supply ports for the domain but it still reports that the power pins are unconnected.

 

[ThisIsNotSam]

I am confused. You say on RTL you leave the port unconnected, but in RTL there are no cells and therefore there are no power ports. Are you confusing netlist with RTL?

In any case, I would look at what ICC does. DC does not necessarily have to understand your power intent if you synthesize blocks individually and only put the power intent together at the chip top level

 

[vince_g]

Still unsolvable for the time being, in the design elaboration phase to create .ddc file do I need to connect the power pins of the instantiated standard cells with power ports?

I think the problem stemmed from elaboration phase since it already reports the unconnected power pin error during that phase.

 

[ThisIsNotSam]

I still don't get what you are saying. RTL should not have power pins. Standard cell pins are recognized by the tools when you provide the cell layout view or abstract (e.g., via a LEF file)

 

[vince_g]

But when instantiating the standard cells for simulations, you would need to have the power pins connected to 1 or 0 logic right? Isn't that in RTL level?

I partly solved my issue by having the std cell power pins connected to dummy nets then connect the dummy nets to the supply nets in my UPF.