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The skid buffer has no "functional" purpose. It is inserted to improve timing, like "normal" pipelining.
The problem is that there is one signal (ready) going in the other direction. To get the full timing improvement, that signal also needs a register. The master will then see the ready signal one clock cycle "too late" when it is set low by the slave.
If there is only one register in the skid buffer, the ready signal going back to the master can only be active for one clock cycle at a time, because the slave can set ready=0 but the master would see it too late.
This means that every second clock cycle the ready going back to the master must have ready=0 even if the slave has ready=1 all the time. The throughput will be cut in half.
The skid buffer with two registers solves that problem. It can accept one more write from the master when the slave sets ready=0.
I do not understand why If there is only one register in the skid buffer, the ready signal going back to the master can only be active for one clock cycle at a time, because the slave can set ready=0 but the master would see it too late. ?
Because the state machines in Fig. 8 are slightly different, so the controllers in Fig. 9 are slightly different (and so are their copies in Fig. 10). Note that the bottom of Fig. 10 is essentially Fig. 9 with the left and right flipped (and one of them also split).
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