zuisti
Advanced Member level 1
Again, these drafts (figures) are not exact circuits, they show only the operation principle.
Study the datasheet carefully, it contains all the necessary info.
However, I'll try to explain this as well:
The upper colored latch contains always the current pin level (clocked with ALL instruction's Q1 phase), while the lower ('mismatch') latch stores that pin level, which at the time of the last RD PORTB was, because its clock (Q3 phase) is gated (enabled) with this signal.
Then both outputs will be XORed, so if they are not the same, the RBIF flag is set (but only when the pin is an input, ie the TRIS latch Q is 1) and we can not clear it until a new RD PORTB is occured.
But ...
Please finish these questions, because there is not much sense.
Sorry.
zuisti
Study the datasheet carefully, it contains all the necessary info.
However, I'll try to explain this as well:
The upper colored latch contains always the current pin level (clocked with ALL instruction's Q1 phase), while the lower ('mismatch') latch stores that pin level, which at the time of the last RD PORTB was, because its clock (Q3 phase) is gated (enabled) with this signal.
Then both outputs will be XORed, so if they are not the same, the RBIF flag is set (but only when the pin is an input, ie the TRIS latch Q is 1) and we can not clear it until a new RD PORTB is occured.
But ...
Please finish these questions, because there is not much sense.
Sorry.
zuisti
