lhlbluesky
Banned
about opamp gain, pls
thanks all, but how to do an lvs_extract? is it equivalent to an 'No RC' extraction?
besides, i find some points:
as the figure shows, the left part is the two nmos pairs of first telescopic cascode stage of the opamp, A B are the source end of the nmos tail current pairs, and they all connect to GND, V1 V2 are the output of the first cascode stage, and also the input of the second stage, as the right part shows. in pre-simualtion, when i connect Vin+ to Vcm+1V (AC)and Vin- to Vcm-1V (AC), DC simulation shows that V1=V2, VC=VD; but due to the current in GND line, the two voltage of A B is different (there is a resistor between A and B), VA=0.6mV and VB=0.9mV; because VB is larger than VA, so VD is larger than VC (about 10mV), and V2 is larger than V1 (about 800mV);therefore, the upper PMOS transistor above V2 enters triode region, and DC gain decreases a lot; when i improve the layout, and decrease the voltage difference between VA and VB from 0.3mV to 0.03mV, the DC gain has a increase of 30dB, but still much smaller than expected; however, to make VA exactly equals to VB is very difficult, ok? i don't konw whether i make my ideas clear, but i expect your answers and suggestions. thanks all.
thanks all, but how to do an lvs_extract? is it equivalent to an 'No RC' extraction?
besides, i find some points:
as the figure shows, the left part is the two nmos pairs of first telescopic cascode stage of the opamp, A B are the source end of the nmos tail current pairs, and they all connect to GND, V1 V2 are the output of the first cascode stage, and also the input of the second stage, as the right part shows. in pre-simualtion, when i connect Vin+ to Vcm+1V (AC)and Vin- to Vcm-1V (AC), DC simulation shows that V1=V2, VC=VD; but due to the current in GND line, the two voltage of A B is different (there is a resistor between A and B), VA=0.6mV and VB=0.9mV; because VB is larger than VA, so VD is larger than VC (about 10mV), and V2 is larger than V1 (about 800mV);therefore, the upper PMOS transistor above V2 enters triode region, and DC gain decreases a lot; when i improve the layout, and decrease the voltage difference between VA and VB from 0.3mV to 0.03mV, the DC gain has a increase of 30dB, but still much smaller than expected; however, to make VA exactly equals to VB is very difficult, ok? i don't konw whether i make my ideas clear, but i expect your answers and suggestions. thanks all.
