Twin well cmos process

[leohart]

twin well process

I'm using twin well cmos process,but it only uses nwell layer for layout,the pwell layer is generated as "Not nwell",which means the sub is pwell if it is not defined as nwell,we cannot get bare psub in layout.

I'm wondering is this kind of twin well process the main stream?Or there is also independent drawing layer for pwell,so we can have nwell,pwell and also psub when doing layout.

 

[elbadry]

triple well process

I think Twin Well means you have a p-substrate that forms the base of your wafer. Above that you grow your own Nwell or pwell by epitaxial growth ( very clean crystallatice ). However, it is almost always assumed that everywhere there is a psub unless you explicitly add an NWELL.

So, at the end of the day you have all the psubs shorted together through the wafer ( p substrate that forms the base ) and you cannot physically build separate n and p wells unless you use a triple well process.

Correct me if I am wrong..

 

[cmos_dude]

n well process

What elbadry has said is correct.
In a twin well process, all the PWells are shorted out throught the PSub. But if you need to have an isolated PWell, you need to use a triple well process with a deep NWell used to isolate the PWell from the PSub.
In that case, you can obtain three different wells viz. "NWell", "PWell" and an "isolated PWell"

--cmos_dude

 

[ashutoshdeenanath]

twin-well process

I think CMOS technology process is twin well process. bcoz if u want to fabricate pmos in p substrate u need a nwell simultaneously when u fabricate nmos u need to pwell. this pwell is not defined by layer but the same layer of nwell can used with negative photoresist, means where nwell there will be a photoresist and doping of p type will happen rest of place. this pwell will be connected through substrate.

 

[leohart]

triple-well process

Thx guys,one more thing to clarify:
Not all twin well process uses expitaxy on psub then form nwell/pwell,some process just bulid nwell in psub,then the psub that havent been implanted as nwell are then implant to be pwell...
so one pwell,seperated nwell...

Added after 5 minutes:

Hi all,I have considering an alternative way to provide isolated pwell in general twin well process...

We can layout a nwell pattern that enclose a pwell inside it,like:

nnnnn
npppn
npppn
npppn
nnnnn
then we get an isolated pwell inside an nwell guardring! Although this kind of isolated pwell is not so perfect comparing what triple well process provides...

What do you think?

 

[leo_o2]

p well process

Yes, the situations about Nwell and Pwell for both epi wafer and non-epi wafer are same. Only difference is the doping for psub.

Added after 5 minutes:

I think your way is similar to triple wells as other people mentioned. The Nwell must be a deep Nwell that should be deeper than isolated Pwell. By the way, another way for isolated Pwell is using N+buried layer with Nwell ring around it.

 

[leohart]

twin well and triple well process in the cmos

hi leo_o2,I was talking about your second way...
In a twin well process,no way to totally enclose a pwell inside nwell...the bottom of the pwell is contact other pwell with psub...

 

[strennor]

triple-well cmos process

i think, if you have NBL, you may have isolated Pwell.


leo_02 is correct