twin well and triple well CMOS process

[fanshuo]

triple well

what are the differences in respect to performance?

 

[khouly]

triple well process

basically the substrate isolation. triple well transistors are more isolated.

khouly

 

[fanshuo]

triple well cmos

yes, there is more isolation,I know that.
Is there anything more?

 

[khouly]

twin well process

i think the triple well is specially used for the RF transistors , which will be used in LNA and VCO and varactors , this is very important , maybe it has a relation with the substarte network in RF CMOS transistor model

khouly

 

[fixrouter4400]

twin well

Hi fanshuo,

Read this article hope this give you more idea about triple well performances.

**broken link removed**

 

[sat]

triplewell

In general MOS devices have 4 terminals D G S B.

B terminal [Bulk/Substrate] has an important role in MOS functionality. From the back-side of a MOS the substrate potential can affect the channel characteristics - it resembles very similar functionality of a Gate terminal of a FET [not a MOSFET but, a Field Effect Transistor], it is called back-gate. You want finer control of the back-gate - go get a triple-well MOS.

We call them isolated-MOS too - the reason being - electrically isolating the bulk node from global substrates.

Although it is not mandatory to keep Source & Substrate connection of a MOS be shorted together, there are design requirements, where the S,B needs to be locally shorted - please note, I did not mention yet - S,B shorted to VDD or GND. Keep it at whatever different potential from global VDD/VSS you need a triple-well process.

Triple well further reduces signal and noise coupling to and from substrate [OK, same as noise isolation].

Triple well might help addressing different potential requirements at IO ESD regions.

Well, somewhere I might have read something about virtual power switching [power-gating] using back-gate [not sure].

All such things are possible by using triple well structures.

 

[fanshuo]

twin well cmos

sat
You mean in triple well devices, it is possible to control bulk/substrate potential?
Because in most case it is not possible, you can only connect the substrate to ground

Added after 1 hours 15 minutes:

by the way, I found that it seems the triple well NMOS has better noise performance than its double well counterpart

 

[pranjal_ccna961]

cmos process

check this out !!!

**broken link removed**

 

[deepak242003]

triple-well process

triple well provide gud isolation ........ low noise substrate noise coupling.. and it is favourable for multiple ground circuits.....

 

[finerain22]

triple well cmos process

Tripple would provide much better LATCH-UP protection over the TWIN well structure.Usually a extra deep N well is implemented underlying the P-Well or N-well, the minority carriers is collected by the reverse biased local (bulk-to-deep N well) junction.