Transition times in CMOS Clock buffer

[sharathpatil]

Hi,
I am trying to design a simple clock buffer to operate at 300 MHz.

What is the normal transition time requirement for the clock signal so that the devices are sized appropriately?

Thanks,
Sharath

 

[dick_freebird]

It has some room for tradeoffs but I'd say you absolutely do not want more than
25% of the period allocated to rising edge and falling edge, apiece, at the worst
case P/V/T corner. The more you care about jitter and skew, the more you will
tighten that up. You will see DFF prop delays drift out as your edge rate slows,
your timing models in the cell library may be predicated on some risetime not-to-
be-exceeded ot the SPICE simulations of Tpd vs Tlh can show you where timing
starts to drift - respect it. The clock buffer's only purpose is to keep the FFs
happy and in step.

 

[patil]

It has some room for tradeoffs but I'd say you absolutely do not want more than
25% of the period allocated to rising edge and falling edge, apiece, at the worst
case P/V/T corner. The more you care about jitter and skew, the more you will
tighten that up. You will see DFF prop delays drift out as your edge rate slows,
your timing models in the cell library may be predicated on some risetime not-to-
be-exceeded ot the SPICE simulations of Tpd vs Tlh can show you where timing
starts to drift - respect it. The clock buffer's only purpose is to keep the FFs
happy and in step.

Hi dick_freebird, thank you for the reply.

Can you please explain how would longer transition times affect jitter and skew (especially jitter)?

 

[dick_freebird]

The slope of your clock is the transform between time
and voltage. Every inverter switches while it is in a
region of linear amplification on the input. Thus any
voltage noise on the input (or supply, PSRR is dismal)
transforms to time-noise (jitter) on the output.

Faster edges reduce the voltage-to-time conversion
factor, and they also probabilistically reduce the
chance of exposing the inverter to sparse perturbations.

 

[sharathpatil]

Thanks a lot dick_freebird. That helps!

 

[vlsiinterviewquestion]

The slope of your clock is the transform between time
and voltage. Every inverter switches while it is in a
region of linear amplification on the input. Thus any
voltage noise on the input (or supply, PSRR is dismal)
transforms to time-noise (jitter) on the output.

Faster edges reduce the voltage-to-time conversion
factor, and they also probabilistically reduce the
chance of exposing the inverter to sparse perturbations.

Primary source of jitter is clock source/PLL and it's independent of slope along clock nodes, but coupling effects on clock will get worse with slow clock slope.

 

[dick_freebird]

You should be so lucky. You can buy a 10pS RMS jitter clock-in-a-can, but
one stupid autorouter decision can give you -many- 10s of pS deterministic
jitter. Been there. If your risetime on internal signals exceeds your source
clock jitter then it's likely to dominate the outcome. All it needs is the wrong
antenna-pair and the wrong signal at the wrong time.