Transistor in triode region as variable resistor

[mvj]

Is the linearity error percentage range of 0.1 to 1 a general figure? This is not mentioned anywhere in the paper.

 

[FvM]

It's an estimation of mine, but 0.56 percent THD has been mentioned, which suggest a similar order of magnitude.

 

[mvj]

May i know the maximum resolution that the DAC can have if it is implemented using the intended method? And may i know how 0.56% THD translates to .1 to 1% non linearity error?

Thanks a lot in advance!!
M

 

[leo_o2]

For high accuracy DAC, transistor working under linear region seems not good in my opinion. Transistor matching should be worse than Poly resistor matching.

 

[FvM]

And may i know how 0.56% THD translates to .1 to 1% non linearity error?

Obviously, translation of linearity to THD depends on the exact shape of the nonlinear characteristic. But the sure thing is, there must be considerable nonlinearity to get the THD. Linearity numbers require a definition, I would refer to a standard INL specification in case of doubt.

Because it's your project rather than mine, you may want to get an overview of the respective relations by calculating some examples with pencil and paper. For a quadratic error term in the transfer function (y = x + bx²), I see a 1:1 relation of THD and INL.

May i know the maximum resolution that the DAC can have if it is implemented using the intended method?

Resolution isn't an issue. But I fear, you won't get much farther than 8 (possibly 10) bit linearity respectively accuracy.