Transistor in triode region as variable resistor

Hi All,

May i know if there is a way to use a trasistor in triode region as a variable resistor with gud control in the resistance value?

THanks a lot in advance!!
M

Yes, it is OK.

Thank you for the reply Leo_o2!!

May i know if there are any papers to refer to.

THanks a lot in advance!!
M

leo_o2 said:

Yes, it is OK.

Click to expand...

It`s OK for FET`s only! Don`t try to use BJT`s for this purpose.

It`s OK for FET`s only! Don`t try to use BJT`s for this purpose.

Click to expand...

Saying "triode region" suggests a FET. But BJT can work (and have been widely used) as variable resistor, if you restrict the voltage drop to e.g. 5 or 10 mV. Operating the transistor in inverted mode also reduces the DC offset. ALC of simple tape recorders is a typical application.

Compared to BJT, FET's allow huge voltages applied to the variable resistor, partcular with linearization. See a previous thread dedicated to JFET. It basically applies to MOSFET as well:
https://www.edaboard.com/threads/129234/

FvM said:

.... But BJT can work (and have been widely used) as variable resistor, if you restrict the voltage drop to e.g. 5 or 10 mV.

Click to expand...

....widely used? I am a bit surprised about that. Please, can you give me an example (link?). Thanks.
LvW

As said: "ALC of simple tape recorders is a typical application" I'm not sure if a have antique schematic as an example.

For my opinion, there are two reasons that do not allow resistor application of a BJT:
* The Ic=f(Vce) characteristicdoes NOT cross the origin (0/0)
* The slope of this characteristic (even for small currents) in the 3rd quadrant is completely different from that in the 1st quadrant.

Thank you for your suggestion FvM!!
Well, i am trying to replace resistors in an R-2R resistive DAC in order to reduce the space consumed, so adding additional resistors( as suggested in the post on using JFET as a resistor) to linearlize the transistor will only increase the space but not reduce it.

May i know if there are any alternative ways to do it..

Thank you very much!!
M

I've seen them being used as LSB in interpolating resistive DACs.
What DNL you get will depend on the FET matching you can achieve.

Bur for R-2R DACs, you generally have more stringent matching requirements,
and it being a current mode DAC, it will be a nightmare when you use low resistances with linear FETs.

I previously overlooked the "good control of resistance value" point. Actually, FET resistance is affected by PVT variations. For "good control" you would want a feedback circuit that sets the gate voltage according to the resistance of a reference transistor. Obviously, it won't give a benefit in terms of chip area. As another point, the linearity of a FET "resistor", with or without linearity compensation, can never compete with the precision resistors used in a R-2R ladder network.

I am planning to implement the resistor using the mechanism mentioned in the paper An Electronically Tunable Linear or Nonlinear
MOS Resistor". Do you still think that i would have any problems?? (Attaching the paper for your reference.)

The primary goal is not to reduce the area alone, the idea is to design a configurable DAC( that can convert 8, 16 and 32 bits as required) using a single 8bit resistive dac. So I am trying to have a mechanism by which i can scale the resistors so as to scale the currents effectively. I do not have control on the input reference voltage so i can not scale it, so i think that scaling the resistors is the only way i am left with.

Please do suggest me.

Thank you!!
M

You can try, but I don't see any potential savings in area or power from using such complex circuitry. Furthermore, the writer has provided no measurements on the linearity of the resistor, short of a graph that shows it "looks" straight. Each resistor also has to be tuned for zero offset (The test engineer would probably kill me on that).

In short, DAC design is all about achieving a certain number of bits while satisfying a decent INL/DNL. If you cannot satisfy the part in bold, a 32-bit DAC is no better than an 8-bit one.

8-bit-linearity is possibly a good guess for the performance of the variable resistor presented in the paper. Although not focussing on linearity, it mentions 0.56 % THD in one place, with a rather low applied voltage, however. I didn't fully understand, how a variable resistor should be used for R-2R DAC designs.

checkmate said:

Each resistor also has to be tuned for zero offset.

Click to expand...

@ checkmate
may i know what you ment by saying "zero offset" and tuning the resistor for that? in the paper( conclusion) it has been mentioned that the resistor has inherent zero dc offset, is it the offset that you are talking about, if so does the problem still exit( since it is mentioned that it has zero dc offset).
Please let me know.

Thanks a lot in advance!!
M

FvM said:

I didn't fully understand, how a variable resistor should be used for R-2R DAC designs.

Click to expand...

@ FvM,

The idea is to use a single 8bit DAC to convert a higher resolution data( say a 16bit data) - i.e. to use two SUB DACs of 8bits each to convert 16bits
Steps involved in the conversion:
1. convert the 8 MSB bits, let the output be Vmsb
2. convert the 8 LSB bits, let the output be Vlsb.
3. To get the correct end result, the output from the LSB conversion "Vlsb" must be scaled by 2^M, where M is the order of MSB sub DAC.
In this case M = 8 so i need to scale the LSB output by 2^8,
and the final output would be Vout = [Vmsb + (1/{2^8})*(Vlsb)]

Now, scalling( i.e. diving Vlsb by 2^8 can be done in 3 ways - theoretically)
1. Scale the input reference voltage by 2^8 for the 8 bit LSB conversion - im not sure how to do this and i have been suggested that it is much easier to scale resistor vaues than reference voltage so i thought not to use this method. Please do let me know if this is much easier than having the head ache of usuing MOS resistors..
2. The second method is to scale Vlsb after the conversion - i could not think of an effective way to do this.
3. The last method is to scale Rf, in the feedback of the opamp, during the LSB conversion - please see the ckt attached to get an idea.



Rf_lsb = (1/[2^8])Rf_msb so that the output voltage gets scaled as required.

So, my idea is to use the third method so taht the LSB output voltage is scaled during the conversion itself.

Regards,
M

FvM said:

As said: "ALC of simple tape recorders is a typical application" I'm not sure if a have antique schematic as an example.

Click to expand...

I realise that the thread has moved on now, but I was prompted to look out an old circuit (designed by Ted Fletcher) for an audio limiter whose active element was the collector-emitter resistance of a simple NPN device. This was widely acknowledged and welcome for its low distortion; quite astonishingly for its simplicity.

I won't post the circuit here (as its not my design) but having looked at it again, I will just add that the active element of the circuit was actually two NPNs (connected rather like a darlington!) with the control voltage applied to the first and whose emitter drove the base of the second. The second device had its collector on a high impedance audio path and emitter on the negative rail.
I'm aware of some similar circuits being used today in 'respected' brands of pro-audio equipment, some of which are greatly favoured over models using much more sophisticated active elements for controlling signal levels!

It's clearly stated that offset is "compensated" by tuning IOC+ and IOC-. No auto tuning mechanism was presented, so I'd assume the tuning was done manually.

As for your intended "scaling" technique, that would imply you would need to scale RF in ratios of 1, 256, 65536 etc. That's quite a big range of scaling that you are looking at, which means your linearity must be maintained over such a huge range as well. I was referring more to Fig 9(a). The key parameter to look at is d(Gm)/d(Igm), which is they key in determining how "accurate" you can tune your resistor. From the figure, I really can't see how many bits of resolution you can get. Furthermore, the resistance, according to the paper, is inversely proportional to Igm, hence non-linear, which would add complexity to your Igm generation.

Ok. The circuit that i am intending to design is a sub block of a chip so i guess there will not be any possiblity to do manual offset compensation, it has to be an auto tuning mechanism. i will try to find some information about auto tuning and see if i can incorporate it into the circuit design. Do you have any suggestions in this regard??

Regarding linearity over a wide range, it is mentioned in the paper that "The linear range of the WLR OTA determines the linear range of the MOS resistor". I have found a paper( attached) which presents an OTA design with increased input linear range VL. Im hoping for this to help reduce the non-linearity issue a bit.
It is also mentioned( highlighted in yellow) in this paper that usage of the high swing improved-Wilson current mirror removes offset voltage adjustment. Is it the offset of the OTA or is he mentioning about something else? If it is the same that we are talking about then i guess there would be no need to add any offset compensation mechanism and that would be really gud..

Please suggest me.

Thanks a lot in advance!!
M

Hi mvj,
I am not quite familiar with your intended application - nevertheless, just one remark:
I think the resistor application of an OTA device (high input and output resistance) is restricted to single end grounded resistors only.

The OTA has only an auxilary function in the said MOS variable resistor circuit. It's designed as a "floating" resistor, of course with a rather restricted voltage range. In my view, it's a more generalized solution similar to the variable JFET resistors discussed in a previous thread. Linearity in both cases is in a 0.1 to 1 percent error range. So it surely has some interesting applications, but rarely for high precision DAC design, as intended by the original poster. The project idea is a helpless case, I fear.