Top level IO cells connection (multiple IO voltages and global source use) and ESD

[dick_freebird]

Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

I have had the pleasure of working for decade in a technology
where the PDK never modeled the GGNMOS clamp's breakdown
action at all, and insisted the GGNMOS clamp PCell was righteous
and inviolable.

Yet ESD results were always very poor.

I had to build my own TLP rig and take my own clamp response
data and fit my own ESD clamp model (trivial really, add a zener
and a resistor to fit bench data in the GGNMOS subcircuit layer
of the modeling hierarchy.

If you have this then you can -design- ESD protection rather
than playing with LEGOs and the set's missing a piece. I'm
talking full pin-pin simulations showing pin I, V to criticize
against what the schematics say is attached.

I made "stinger" macros parameterized such that parametric
analysis nested loops (of pin# indices) can perform the
pin-pin combo zapping and show a "worst case envelope"
when plotted. Loop pinX, pinY and zapPolarity and go have
lunch and a nap.





An actual adjunct breakdown model:
Kill all the forward params and tweak the reverse breakdown to fit
bench waveforms from TLP

simulator lang=spice
******************************************************************
* Clamp breakdown model with series resistance*
* area normalized to w=1um at area=1 *
******************************************************************
.model dzGGNMOS Diode
+Level = 1
+IS =1E-99
+ISW =0.00
+N =99
+NS =1.0
+IMAX =1.0
+RS =1400
+RSW =0.00
+BV =4.7
+IBV =1.00E-05
+NZ =6.0
+TRS =3.47E-03
+CTA =0.00
+CTP =0.00
+EG =99.9
+XTI =9.8056
+Cjo =1E-18
+Mj =0.0627
+Pb =0.173
+Cjsw= 0
+Mjsw= 0.33
+vjsw= 0.7
+Pta= 0
+Ptp= 0
***********************************************************

 

[NikosTS]

Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

Wow thanks for the answer dick_freebird, it will take some time to process this!
@dr_kca , i will let you know when i get an answer. As far as the test is concerned, the signal pin is connected lets say to the gate of a MOS. This node, that i measure the overvoltage due to the ESD event , is also the cathode of a diode which also connects to the ground as well as the anode of a diode which also connects with the supply rail. Isnt it normal for that node to have an overvoltage due to ESD, which will quickly drop to acceptable voltage level? Have i misunderstood something?

 

[dick_freebird]

Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

Of course there will be a transient overvoltage, and this
had best be limited to an envelope that the "victim" can
withstand - without either evident or latent damage. The
latter is a big concern for a parts vendor's production as
it can result in passing units that become field returns
(failed in system). Yet latent damage is difficult or even
impossible to detect by immediate testing, requiring a
long term life test in conditions that could be expected
to expose or accelerate the damage evolution.

So yes, it's "normal" and no, it's not "helpful" - whether
or not it's harmful, you have to get specific and know
both the technology reliability limits and the threat
signature as seen by each bit of the "guts" (which
each may have different sensitivities based on the
connection and construction of each device).

Gate oxides can stand much more voltage for a
microsecond, than you'd see rated based on long
term stress testing. But how much more, is an
exercise that manufacturers resist performing at
all, and publishing even more so (it only encourages
tourists to stand closer to the cliff edge).