To add to the last reply, Digital PLLs are only good for speeds not exceeding 250Mhz mostly because standard digital cells do not run faster than 500Mhz reliably and even at thos speed have excessive jitter. So if you need higher speeds design your vco and filter in anlog and your divider circuit needs to be designed using custom cell design techniques so you get the duty cycles close to 50/50. For lower speeds, use DCO instead of VCO and all other blocks can be digital. Consider analog filters since they are usually smaller than digital filters for lower speeds.