[SOLVED] TLP test boxes for ESD protection devices

[prcken]

hi all
do you have experinece in using high voltage (e.g. 3.3V) device as ESD device for low voltage(e.g. 1.8V/1.2V) device domain protection?
usually, from circuit design perspective, he/she will not connect 3.3V device to 1.8V/1.2V power supply.
i saw the 1.8V power clamp ESD device failed in several projects. while 3.3V power clamp never failed.
i dont think there is a problem if 3.3V device is used as ESD protection device for 1.8V or 1.2V power pin, in normal operation, the ESD device wont work, while, in ESD event, it's more robust than low voltage device.
any comments?
thanks!
-Kehan

 

[dick_freebird]

ESD discussion

You need a clamp that will conduct the full ESD threat current,
at a voltage lower than the weakest device's fail voltage.

Figure a 3.3V rated transistor ought not break down below
4V, and might have 1-2 ohms of post-breakdown current
(for a net 7-8V of peak ESD hold-down voltage).

How does 8V play, against your 1.2V (likely BVox, under 5V)?

If your power clamp fails in itself, look to the physical design -
hot spots, needing more pullback of contacts? I/O devices
(like the 3.3V clamp) might embody these pullback rules,
while core devices would not.

If your clamp survives but the "protected" circuitry does
not, it may be more a problem of inadequate width or other
circuit / scaling problems. Such as, trying to protect 1.2V
transistors with a dual-ring, central clamp scheme adds two
more diodes (at at least 1V apiece) to the total clamp
voltage, which helps less than not at all.

It is possible to build yourself functioning ESD device models
even if your foundry does not choose to provide them.
If you have that, and the detailed knowledge of failure
thresholds, you can design ESD protection just like you do
any other circuitry - goals, limits, result, repeat.

 

[prcken]

Re: ESD discussion

You need a clamp that will conduct the full ESD threat current,
at a voltage lower than the weakest device's fail voltage.

Figure a 3.3V rated transistor ought not break down below
4V, and might have 1-2 ohms of post-breakdown current
(for a net 7-8V of peak ESD hold-down voltage).

How does 8V play, against your 1.2V (likely BVox, under 5V)?

.....

hi dick_freebird
thanks for your detailed explanation.
yes, that's the problem, i have no TLP results for comparison, i have test data for the 1.8V power clamp shows a relatively high clamp voltage at 5V when the ESD current is at 1A, the turn-on resistance is relatively large. Gate Coupled NMOS (GCNMOS) is a non-breakdown mechanism (no snapback I-V curve), the key point need to be watched is turn-on resistance in power clamp ESD design, so i think both 3.3V or 1.8V device can be tuned well for 1.8V core circuit protetction. maybe 3.3V device is more robust at ESD event.

 

[dick_freebird]

ESD discussion

I have made my own TLP test boxes. You can get useful ESD
emulation at only a few hundred volts. It takes a roll of coaxial
cable, a mercury-wetted relay, a high value feed resistor
and an output resistor of slightly less than line impedance.

One end of the line is open.

The other end connects the core to HV through the high value
resistor (100K or so), and to the relay NO contact through
the (say) 47 ohm resistor. Relay COM and line shield are your
"stinger".

Put a 1-ohm sense resistor in the return leg and you can
read current on the 'scope probe. Another probe to the hot
side and you have a voltage that equals Vclamp+Iclamp.
You can subtract those in postprocessing if your 'scope
will export a .csv file.

Running a series of line voltages you can determine where
things fail, pretty plainly. Total cost for such a jig is under
$100. Just don't let OSHA catch you using it....

Gate coupled NMOS, like where you have a large value gate
resistor to ground, depends on a high edge rate to energize
the gate. But the gate voltage can bleed off quicker than the
HBM charge )time constant 1.5K*100pF, you need many,
many tau before residual charge has bled below (say) 5V
at the source. Too low a resistor will release the ESD source
before it's discharged. But everybody wants to cheap out
on area so standard designs are liable to be "barely good
enough" (for somebody).

 

[prcken]

Re: ESD discussion

I have made my own TLP test boxes. ................." (for somebody).

hello dick_freebird
That’s awesome. I am interested in your DIYed TLP system. i drew a picture according to your description which is attached. did i draw it right? i think this configuration is called current source TLP,
and i have some questions as below:
1.Relay COM and line shield are your \"stinger\".
Q1: how this stinger works? I meant in order generate a square pulse of selectable duration and amplitude, the distributed capacitance of cable should be charged and discharged. How to do it automatically, or just manually?
Q2: how does the relay works? At first, it should connects the HV box and one end of the coaxial cable, and after it charged (how do I know it is fully charged?), it should switch this end of the coaxial cable to a 47ohm resistor as your mentioned to generate the pulse.
Q3: Put a 1-ohm sense resistor in the return leg to read current on the scope probe. How to do that? The 1-ohm sense resistor should be in series with DUT, I think I have drawn it wrong in the picture.
Q4: did you put another relay or switch to measure the leakage after each pulse?
Q5: Total cost for such a jig is under $100? So cheap? HV box and oscilloscope are not included in the budget? I heard that made TLP will cost nearly 1 million RMB, which equals to about 15k US dollars or so. And I don’t think there is OSHA in China
thanks for you answer in advance
-Kehan

 

[dick_freebird]

Re: ESD discussion

Cost is low because there's very little to it. A cast-off enclosure,
a 50' box of 50-ohm cable, a mercury relay, a momentary switch
and a small number of resistors.

Now, if you -had- to have 10kV capability, an arbitrarily large number
of relays to do full pin-pin on complex ICs, embedded control and
the sorts of pre/post pin measurement that "professional" rigs offer,
not to mention a whole mess of compliance, safety and accuracy tests,
it would get much more expensive.

But I built it to do one job, which was to test the available ESD clamp
device in a pulsed mode, accurately enough to hack a model for it.

If you are looking at "5V" devices then you don't need 10kV, you
need only apply a realistic current pulse with more than enough
voltage compliance to get it. 200V/50ohm equates to about a 6kV
HBM pulse, current-wise.

Some doc pics I saved from when I built it:

 

[paulsong08]

Re: ESD discussion

You are a genius。
But the voltage waveform oscillation is obvious. It seems rather than a waveform from HBM.

Cost is low because there's very little to it. A cast-off enclosure,
a 50' box of 50-ohm cable, a mercury relay, a momentary switch
and a small number of resistors.

Now, if you -had- to have 10kV capability, an arbitrarily large number
of relays to do full pin-pin on complex ICs, embedded control and
the sorts of pre/post pin measurement that "professional" rigs offer,
not to mention a whole mess of compliance, safety and accuracy tests,
it would get much more expensive.

But I built it to do one job, which was to test the available ESD clamp
device in a pulsed mode, accurately enough to h(at)ck a model for it.

If you are looking at "5V" devices then you don't need 10kV, you
need only apply a realistic current pulse with more than enough
voltage compliance to get it. 200V/50ohm equates to about a 6kV
HBM pulse, current-wise.

Some doc pics I saved from when I built it:

 

[dick_freebird]

ESD discussion

The purple waveform (current) rings quite a bit. Not sure how
much is due to the rather long leads on the "zap" side, or how
much of the ringing could be taken out by a cleaner line match.

The intent of this box was not to replicate the human body
model in detail (or even, at all). What I wanted was the ability
to pulse-stress ESD clamp cells at a relevant current
so that I could determine the post-breakdown resistance
and fit a functional model for designing larger networks.

 

[prcken]

Re: ESD discussion

Hello, dick_freebird
Thanks for your share. I have updated the TLP picture accordingly. Is this time right?
High voltage box is always connecting to one end of the coaxial cable, after the cable finished charging, S1 should be closed, how do I know the cable is fully charged? And I think S1 is controlled by S2 of the relay automatically, so how do I control S2?
-Kehan

 

[prcken]

Re: ESD discussion

The purple waveform (current) rings quite a bit. Not sure how
much is due to the rather long leads on the "zap" side, or how
much of the ringing could be taken out by a cleaner line match..

"high parasitic elements at the DUT slow the achieveable dV/dt and increase the probability for ringing." quoted from the book entitled ESD in silicon integrated circuits – second edition. 2002: John Wiley & Sons, Ltd by A. Amerasekera and C. Duvvury, page 53.

 

[dick_freebird]

ESD discussion

S2 in my box was just a SPST-NO pushbotton switch. The charging
time, I did not control especially. On the bench I spent so much
time peering at the 'scope and exporting waveform files that
I was sure the line charger fully. You could calculate the
Cline*Rcharge time constant from cable specs and run out to
a few tau. But megohms times picofarads is only microseconds.

You could replace S2 & DC5V with a 5V digital relay driver
resource if you were looking to automate.

I left the far end of the line open, do not know what the diode
is for. I did not have a second Tline (the clip-leads are some
sort of line, but impedance is totally not controlled).

 

[prcken]

Re: ESD discussion

...I left the far end of the line open, do not know what the diode
is for. I did not have a second Tline (the clip-leads are some
sort of line, but impedance is totally not controlled).

yep, i noticed that you left the far end open. i read some other reference( http://www.ics.ee.nctu.edu.tw/~mdker/ESD/index/index5.html this is written in traditional Chinese by Prof. Ker) in which it said this schottky diode could quickly remove negative reflected wave. actually i am not quite understand.

i did simple simulation with hspice with the far end open. i have attached the simulation results. do you know how to get relatviely accurate W-element U model form of RG58 coaxial cable?
it's obvious the pulse width is not 100ns for this 10m length cable, maybe my cable model (i used rlgc model) is too far away from RG58.
what's more, the amplitude of the pusle is only 45V or so, but my source voltage is set at 100V, the impedence is poorly matched.

 

[prcken]

Re: ESD discussion

i found the rg58 model in hspice and re-simulate it, got the pulse waveform, it looks right.
the pulse width is about 100ns with ringing.
the voltage is half of Vsource when the switch is closed due to 50ohm termination. and the waveguide propagates back and forth through the coaxial cable so that 100ns pulse is generated.
so 100V voltage source only got 50V pulse.
dick_freebird, am i right?

 

[xiangxianga396]

Re: ESD discussion

Most times you can't use HV power clamp for your LV power rail protection, because HV power clamp maybe can't turn on even your internal circuit fail with LV power.

 

[prcken]

Re: ESD discussion

Most times you can't use HV power clamp for your LV power rail protection, because HV power clamp maybe can't turn on even your internal circuit fail with LV power.

yes, there is a potential problem as you said, provided that fast triggering and low clamping voltage feature, i think no probelm to use HV device for protecting LV core-devices.

 

[Teddy]

Re: ESD discussion

I am no ESD expert and designed just a handful of my own esd protections but I would try to avoid it. If you are not using 3.3V (or any other HV) devices in your design then you are going to increase price of the wafer for about $50-$100 just by adding the ESD protection in HV devices - not worth it. Each fab has their ESD recommneded rules - not the best unles you pay but you can tweak the devices based on your experience. If you use silicide block and ESD diffusion you will be fine with LV devices.