TI's White LED Driver TPS61165

[aryajur]

tps61165

Hello attached is the datasheet for TI's TPS61165 part. The EC table shows that the source and sink currents at the comp pin i.e. at the output of the Error amplifier are 100uA which means the output stage of the Error amplifier is biased with 50uA. The next specification is the transconductance of the error amplifier which is given to be 320uS.
Now if their output stage source and sink currents are mismatched by say 5% which means 2.5uA then the offset at the input will be
Vos = 2.5uA/320uS = 7.8mV

But this would then cross over their accuracy specification of 2%. So I am interested in discussing whats going on here. Are they trimming their output stage current source and sink to match very accurately, or is there some problem with the datasheet or am I interpreting it wrong?

 

[leo_o2]

white led vf at 50ua

No. The current accuracy of EA will not influence the current offset because it is regulated by the feedbackloop.

 

[aryajur]

circuit ideas for tps61165

Yes of course it is regulated by the feedback loop but there will be an offset if the source and sink currents are not matched. Let me explain better, see the attached figure for reference. Suppose the source bias current in the output stage is 52.5uA and the sink bias current in the output stage is 50uA. Now when the loop comes to regulation then ideally the inputs of the error amplifier will be at the same voltage of 0.2V which is the reference voltage. This means input to the error amplifier is 0, and now since the source and sink currents are mismatched the output cap at COMP pin will start charging with the 2.5uA of net current. This would increase the output of the error amplifier which would seem to the PWM controller that there is not enough current in the output string thus will try to increase the current. The increase in the current will cause the Feedback voltage to increase and become greater than 0.2V. Then it becomes 207.8mV at that time the net input voltage to the error amplifier is 7.8mV and this would cause the source current and the sink currents to equalize thereby making the COMP pin regulate at a fixed voltage. So now this is the regulation state. And its clear that during regulation there is an offset of 7.8mV degrading the accuracy of the chip.

 

[leo_o2]

what is a tps61165

No. In actual design, they are not two individual Isource and Isink. They are output of a OTA. First, the mismatch will never be so big. Second, the loop will automatically set the dc operating point for the node "comp". At the stablized operating point, Isource will be exactly equal to Isink according to unbalanced Vds of Isource and Isink.

Added after 2 minutes:

Of course, the mismatch of input pair will still exist.

 

[aryajur]

tps61165 forum

I don't see why they are not individual Isource and Isink. Would you please show some ideas which make a source sink output stage without having a source current and sink current separately? Also the mismatch can be easily be this much if the system is not trimmed in a special way. If you design a MOS current mirror and want smaller Vdsats 5% of mismatch in the mirrored currents can very easily happen. Also the current is translated to the high side and mirrored by PMOS in the source side and mirrored by NMOS in the low side to make the sink. So now this should make the Mismatch even worse because usually there will be scaling in the mirror to have such a high current.
Also as I explained in my previous post, the loop definitely regulates and as you said at that time Isource and Isink are exactly equal. That is true but what is forcing them to be equal? Its the input to the error amplifier. It is obvious that if they are not equal with 0 input then you definitely need some kind of input to make them equal and thats how offset is defined, isn't it?
ANd then of course mismatch of the input pair will also contribute definitely plus the mismatch of other transistors in the amp.

 

[ynhe]

tps61165 c code

Hi aryajur:
The offset of E/A can be seen as disturbances or distortions.
But it is in the loop of negative feedback.
Feedback reduces the line-to-output transfer function by a factor of 1/(1+LG)
LG is open loop gain.
if dc of LG is 60dB,the offset of E/A could reduce 1/1000.
So you do not worry about mismatch of E/A too much.


Ynhe

 

[aryajur]

tps61165 issues

Sorry for my absence from the discussion. We can resume the discussion now. I see that there is still disagreement that there will be a severe offset problem in the system if the current source and sink are not trimmed. To prove my point I would suggest running a simulation.
The following netlist represents the sytem macromodel as represented in the schematic image.

*Spice netlist for Circuit: TPS61165.CKT
V5 Is1_2 C1_2 DC 0V
V4 Is2_2 0 DC 0V
D4 D3_2 VcIs1_1 DLED1
D3 D2_2 D3_2 DLED1
D2 D1_2 D2_2 DLED1
D1 U1_6 D1_2 DLED1
V3 Is1_1 0 DC 5V
V2 U1_2 0 DC 1.23V
EU1 U1_6 0 C1_2 U1_2 1E5
Is2 Is1_2 Is2_2 50u
Is1 Is1_1 Is1_2 52.5u
C1 0 C1_2 10n
V1 VcIs1_2 0 DC 0.2V
GVcIs2 Is1_2 Is2_2 VcIs1_1 VcIs1_2 160u
GVcIs1 Is1_2 Is1_1 VcIs1_1 VcIs1_2 160u
R1 0 VcIs1_1 0.57
.IC V(C1_2)=0v
.SAVE Is1_2 C1_2 Is2_2 Is1_1 VcIs1_2 VcIs1_1 D3_2 D2_2 D1_2 U1_6 U1_2 @v5[p]
.SAVE v5#branch @v5[z] @v4[p] v4#branch @v4[z] @d4[p] @d4[id] @d3[p] @d3[id]
.SAVE @d2[p] @d2[id] @d1[p] @d1[id] @v3[p] v3#branch @v3[z] @v2[p] v2#branch
.SAVE @v2[z] @is2[p] @is2[v] @is1[p] @is1[v] @c1[p] @c1[i] @v1[p] v1#branch
.SAVE @v1[z] @r1[p] @r1[i]

* Selected Circuit Analyses :
.TRAN 20n 100u 0 20n UIC

* Models/Subcircuits Used:

*LED1 Typ RED GaAs LED: Vf=1.7V Vr=4V If=40mA trr=3uS
.MODEL DLED1 D (IS=93.2P RS=42M N=3.73 BV=4 IBV=10U
+ CJO=2.97P VJ=.75 M=.333 TT=4.32U)
.END

I have given a mismatch of 2.5uA between the current source and sink. The result of the transient simulation will clearly show the 7.81mV offset at the error amplifier input as was calculated above in my post.
The node above resistor R1 shows it to be settled to a voltage of 207.81mV.
The analysis given by ynhe is not applicable to offset voltage since it is not a separate signal that is being injected into the system, it is the property of the system that is a part of its operating point settling. Even if you consider it as a signal the offset effect in open loop is infinite because of the integrator so the loop does divide it down and give you a net 7.81mV offset.
I hope this explantion would better present my point.

 

[maxmianyang]

current mirror led driver

i think when the system is regulated.In every duty cyclw,(the sink current*sink time)=(source current*soucr time).The sink current do not equal the soucre current do not matter.