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Place&Route using SoC encounter
Hi all,
1) Could you please let me know how can I consider timing-related constraints on place and route. In DC when we are performing synthesis, we can put a kind of constraint on the maximum delay between inputs and ouputs (e.g. delay between in1 and out1 not exceed X ps). I am wondering if there is a similar method in encouter?
2) I forced my DC to meet the delay limit. but I cannot reduce the delay beyond an specific point. Is there any way to resolve the problem by place&route?
Thank you
Victor
Hi all,
1) Could you please let me know how can I consider timing-related constraints on place and route. In DC when we are performing synthesis, we can put a kind of constraint on the maximum delay between inputs and ouputs (e.g. delay between in1 and out1 not exceed X ps). I am wondering if there is a similar method in encouter?
2) I forced my DC to meet the delay limit. but I cannot reduce the delay beyond an specific point. Is there any way to resolve the problem by place&route?
Thank you
Victor
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