Thermometer to binary encoder

[mrflibble]

Sure you can use an MMCM in your design. Do you still intend to do the wave union thing? If so how are you going to trigger the oscillator. So for a TDC without ring oscillators: yes. With ring oscillators: no use, except for the sampling clock.

 

[Jetach]

If I were not use a TDC without a ring oscillator, it doesn't seem to be feasible to get a 10-100 ps resolution.

However, using a MMCM would keep the delays consistent as opposed to it fluctuating due to the delay chain changing based on temperature.

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Another question, how can I used true code (not timed delayed) so that when I run a simulation the delays from the carry chain will produce hardware implemented results.

Once I get that solved, I need to figure out how to preserver the carry chain otherwise it get becomes eliminated by the optimization tool.

Thanks for all the help so far mrflibble

 

[mrflibble]

100 ps? pfffffrt. 10 ps, yeah that's the tricky part of the 10-100 ps range.

I didn't use an MMCM for delay compensation, but maybe you come up with something clever. So don't let my opinion get in the way of progress! Try it and let us know what works and what doesn't.

As for simulation ... expect pain. XD You'll have to do post place & route simulation and long runs to get something useful. Also, run it in real hardware with some nice bandlimited white noise on the input, capture your TDC outputs, collect all those TDC outputs in a large file and do something clever.

Preventing optimization: lots of KEEP and SAVE attributes. Also, see the xilinx constraints guide.

And I noticed in the latest paper that they upped their game, the b4stards! Now I will have to get me one of those parallella boards and set aside a few weeks coming winter to see if I can do better.

Do you happen to know how the ZYNQ-7010 carry chains compare to that of a spartan-6? And on the subject of specific fpga's, what fpga are you implementing this on? Virtex-6, or something even more expensive?

 

[Jetach]

My company wants to start using the kintex-7, however since it is such a new fpga, there is very little research done on TDC's for the kintex-7.

I would hope that the carry chain delays are just improved and the general design would be the same.

As of right now I am having a bit of difficulty getting the delays from the carry chain to execute properly.

Also worried that my work may be completely irrelevant if the kintex-7 has a different way of implementing the delay chains

 

[mrflibble]

I think carry on kintex-7 is going to be pretty much the same as carry on the previous family. Not 100% sure since I haven't gotten my hands on any kintex-7 goodies yet. When I do, I'll port my current TDC design and see how that goes.

 

[Jetach]

As of right now, I have been creating timed delays on the in the mux for the carry chain adder, because otherwise iSim runs the code immediately without any delay... I am wondering if there is anyway to simulate it onto hardware.

I am creating a small scale version with only 8 delay chains being utilized.

There is a lot more I need to learn and become familiar with VHDL.

 

[mrflibble]

Well, like I already said ... to simulate it you'll have to synthesize it and then run a post place & route sim. That will get you something fairly close to what really happens in hardware.

And by "8 delay chains" I take it you mean 8 taps aka 2 CARRY4's.