When a bipolar transistor is saturated its no longer in a linear state.
View attachment 191575
I must disagree with the numerous misleading plots on the web that incorrectly define the saturation region for common emitter BJTs. The confusion is compounded by the fact that FETs have an opposite behaviour, where their saturation region resembles the active region of BJTs.
Although it may seem harsh or unbelievable how many online examples of this oversight exist, it is impossible to operate within the striped zone above, except along the straight line that limits the switch's lowest resistance. But it we call everything below Vce=2V for most transistors at max current as "saturated" I suppose the cause of the error can be understood. But it is certainly not possible to achieve Vce< Vce(sat) with the same test conditions. It is only by exceeding input current and lowering output current can this be achieved with very little gain. So in effect, the zone is projected with different assumptions than the definition of these plots or the definitions of Vce(sat).
You can get Vce=0 with an open circuit, but it is not the same as low R switch.
The "bipolar saturation zone" is the transition zone from a small resistor limit to a very high resistor limit, with the collector acting as a current source/sink, which then becomes the active region for quasi-linear amplification. This zone excludes many incorrect representations of the saturation region. It is defined by the vertical slope of
RCE(SAT)=VCE(sat) / IC, operating as a switch with a certain
Ic/Ib ratio. The constant
Ib plots show the transition to higher
Vce values, moving from a switch to a high-impedance current source. The output high impedance is characterized by the almost flat slope of the constant
Ib plots.
All transistors inherently exhibit nonlinear quadratic behaviour, which can be approximated as linear (quasi-linear) with errors measured by THD or the percentage peak gain of an AC signal. The plot mentioned is misleading, incorrect, and commonly found online, even on sites like Electrical Stack Exchange.
This information is rarely quoted in datasheets, except by Diodes Inc. for their ultra-low
VCE(sat)"super beta" transistors with very high Beta or h
FE. These patented designs have low
RCE(sat)=VCE(sat) / Ic . I will not detail thermal effects in detail, except to note that diodes and BJTs are neg. tempco. or NTC and run faster with lower resistance when hot. This is a natural characteristic, though not a recommendation to run them hot. Meanwhile, Vce(sat) vs temp is more complex with Ic and hfe. being somewhat parabolic.
Facts
The actual saturation region is a quadratic zone between the linear Rce and any chosen corner curve asymptote of the constant Ib curves. Beyond this is normally called the active region for amplification with the best linearity. It should be noted that this online plot had very small collector currents, and the so-called collector leakage currents do not show up. They manifest as the slightly elevated slopes pointing backwards to Dr. Early's intercept voltage, projected to fictitious negative voltages where Ic=0 and is known as the "Early Effect" or just Rce leakage resistance.
The choice of the corner depends on your tolerance for THD or total harmonic distortion from the nonlinear behaviour at low Vce. This corresponds to a full-swing negative peak at the collector. For high-power amps, a minimum Vce of 2V is recommended to avoid high current distortion, but for a switch, this would be a lossy operating point. Therefore, for switches, R
CE(sat) is computed from the datasheet limits, projecting the current to estimate Pd max.
P
d(sat) = V
CE(sat)×I
C.
An interesting application of the saturation zone is shorting the base-collector nodes as a diode, where the collector current still follows Vbe and amplifies Ib but with lower hFE values. The Ic/Ib ratios used to define V
CE(sat) range from 10, 30, 50, to 100, with 10 being the most common and higher ratios for superbeta types (hFE 300 to 3000+). However, very high beta and low Rce come with higher capacitance and increased noise unless gold-doped, leading to higher prices than standard BJTs.
Standalone transistor amplification is not highly linear; some transistors are more linear than others and are used in audio or power amplifiers. However, feedback can significantly reduce nonlinearities to acceptable levels.
It is easy to achieve 10% distortion on any H-biased amplifier in full-swing by measuring the difference in ±Vpk/Vavg * 100% closely approximates %THD from non-linearity.
Here is another definition of the Saturation Zone where Vcb>0 is forward biased. This imples Vce<= Vbe which contradicts the plot above when Vce=2V with AC distortion threshold at max. DC current as you would not operate Vbe at 2V. There are differences in the transistor models for Rce, Rcb, and Rbe that are not as big as the current gains and this is why Vce saturation region voltages are extended to more linear Active region.
Now getting back to a rephrased version of the original question.
Where is large swing pulse voltage delay the worst? Saturated region or Active Region?
Clue: Where is RC=Tau highest? Which parameters affect C and which affect the effective output impedance? Vbe, Rce, Vce, Vbe, Reverse recovery time model, etc...?
Hint: the biggest effects are reverse recovery from full saturation and then Miller effects dominate due to junction capacitance between collector-base.
Since C maximizes towards PN junction=0V and onward into the forward-biased region this is when Vce reduces to Vbe and is typically < 0.7.
Thus avoiding as much of the Saturation Region as possible at the expense of heat rise, improves pulse delay time and rise time.
The plots discussed so far was for a common emitter (CE), which trades off BW with gain. So naturally configurations like CB and CC are faster for switching and current mode switching is by far faster than voltage mode switching as in ECL, CML.
Conclusion
Lowest CC pulse delays avoid saturation region as much as possible with the minimum as
@dick_freebird suggested.