testing pulse delay in saturation and active states of a NPN

[yefj]

Hello,I want to test the delay of a pulse when NPN is saturated and non saturated state.
I know it depends on the level of the pulse.
From the datasheet and abothe manual i have tried to recreate the state oj the junctions.
At first EB junction must be forward. I have tried to build the circuit below.
As you can see the BE junction is active,also you can see the Vce is very high.
Base current and collector current are attached.
How do i know if my NPN is saturated or active acording to the datasheet attached?
LTspice file is attached.

Datasheet for 2N2369 Motorola Transistors | Octopart

View and download the latest Motorola 2N2369 Transistors PDF Datasheet including technical specifications

octopart.com

https://www.ece.mcgill.ca/~grober4/SPICE/SPICE_Decks/1st_Edition_LTSPICE/chapter4/Chapter%204%20BJTs%20web%20version.html

 

[danadakk]

Its not in sat, Vcesat should be ~200 mV at Ic of 200 mA. And Ibase for Icesat of 200 mA should be ~ Ic/10 or 20 mA

Your issue is your emitter R is fighting you from developing enough base drive, and you are running this transistor
close to its max ratings....

From Phillips Datasheet :

 

[yefj]

Hello Dana,How do i lower the Vce, I got the VBE 0.8 so its open.
However when i increased the resistors i couldnt see any Vce decrease as shown below.
Where did i go wrong?
THanks.

--- Updated Jun 14, 2024 ---

UPDATE:

Hello, I made Vce=0.2V as shown below.How do i know that my NPN is in "active" linear(mosfet) state?
Thanks.

 

[danadakk]

Play with Ic, and Base Drive and speedup cap. Here Vcesat = ~ 300 mV

When a bipolar transistor is saturated its no longer in a linear state.

 

[yefj]

Hello,I got Vce 200mV as shown below.
given the data sheet in the link belo how do i know that my npn moved from saturated to active (linear) state?
Thanks.

Datasheet for 2N2369 Motorola Transistors | Octopart

View and download the latest Motorola 2N2369 Transistors PDF Datasheet including technical specifications

octopart.com

 

[danadakk]

More on sat (generic transistor)

Look at characteristic curves, when there is a linear relationship between Ic and Ib.....

Ic = beta x Ib

 

[yefj]

Hello Dana,There is no such plot in the datasheet,there are no plots at all.
waht datasheet you use and what is the number of the plot for linear state?
Thanks.

Datasheet for 2N2369 Motorola Transistors | Octopart

View and download the latest Motorola 2N2369 Transistors PDF Datasheet including technical specifications

octopart.com

 

[danadakk]

The plots i showed are generic plots, just to show general info.

Except the test circuit from the Philips datasheet.

Attached is Fairchild DS.


Regards, Dana.

 

[FvM]

If understand right, your saturation considerations are focussed on switching time (toff). In this regard, saturation can be defined as the point where Ic/Ib drops, the knee in post #6 upper diagram curves. Transistor base zone is filled with additional charge carriers, they have to be removed to turn Ic off.

 

[danadakk]

If, as FVM states, you are concerned with speed use Baker clamp :

Baker clamp - Wikipedia

en.wikipedia.org

Or use speedup capacitor :

Regards, Dana.

 

[yefj]

Hello, I want to recreate post 6 Ic/Ib knee plot .What it the Voltage Y axes meaning ?
Also what is the strategy for creating such plot ?
In gm_id plots in mosfet have gm vs vgs and Id vs vgs .
What is the plot building strategy in here?
Thanks .

 

[danadakk]

So what is constant in this plot, what is varied, and what is measured ? All clues how to set up sim.

 

[yefj]

Hello,In the plot below there is the saturation region.
it looks to me exactly like the linear region of mosfet.
What exactly in the linear plot we can call saturated?
Thanks.

 

[danadakk]

 

[dick_freebird]

B-C and B-E forward biased is the definition but the
B-C forward bias -current- defines the stored charge
and the storage time. You can forward bias B-C by
300-400mV (at room temp) and not pay much of a
turnoff-time penalty, this is why LSTTL & STTL. Baker
operates similarly but using diodes with their own
storage times and at least one of 'em as high voltage
as the NPN application peak (unless you want the
B'-C Baker device to intiate a boosted clamping or
something).

So set yourself up for -realism- and one eye on B-C
current (you can get this in simulation, or record all 3
terminal currents and do curve arithmetic). Then you
can make yourself a storage time test jig and set up
for the load and see what the base current waveform
looks like, which shows you storage time.

 

[yefj]

Hello Dana, If we compare to the definition of saturation in mosfet.
That means because of pinch off there is no futher increase in Ids current no matter the increase of Vds.
Where as we have the bjt definition shown below they say that its condunction heavily .
What is conducting heavility means on the plot?
Why the active reagion plot platoe shape soesnt means that its conducting heavily?
Why the linear rise in Ic current means that its conducting heavily?
Thanks.

 

[danadakk]

Here is an interesting video on topic :

Conducting heavily means large Icollector current even though Vce is low. Good
description at chatgpt.com, type in :

"What does conducting heavily mean in terms of bipolar transistor in saturation"


Regards, Dana.

 

[D.A.(Tony)Stewart]

When a bipolar transistor is saturated its no longer in a linear state.

View attachment 191575

I must disagree with the numerous misleading plots on the web that incorrectly define the saturation region for common emitter BJTs. The confusion is compounded by the fact that FETs have an opposite behaviour, where their saturation region resembles the active region of BJTs.

Although it may seem harsh or unbelievable how many online examples of this oversight exist, it is impossible to operate within the striped zone above, except along the straight line that limits the switch's lowest resistance. But it we call everything below Vce=2V for most transistors at max current as "saturated" I suppose the cause of the error can be understood. But it is certainly not possible to achieve Vce< Vce(sat) with the same test conditions. It is only by exceeding input current and lowering output current can this be achieved with very little gain. So in effect, the zone is projected with different assumptions than the definition of these plots or the definitions of Vce(sat).

You can get Vce=0 with an open circuit, but it is not the same as low R switch.

The "bipolar saturation zone" is the transition zone from a small resistor limit to a very high resistor limit, with the collector acting as a current source/sink, which then becomes the active region for quasi-linear amplification. This zone excludes many incorrect representations of the saturation region. It is defined by the vertical slope of RCE(SAT)=VCE(sat) / IC, operating as a switch with a certain Ic/Ib ratio. The constant Ib plots show the transition to higher Vce values, moving from a switch to a high-impedance current source. The output high impedance is characterized by the almost flat slope of the constant Ib plots.

All transistors inherently exhibit nonlinear quadratic behaviour, which can be approximated as linear (quasi-linear) with errors measured by THD or the percentage peak gain of an AC signal. The plot mentioned is misleading, incorrect, and commonly found online, even on sites like Electrical Stack Exchange.

This information is rarely quoted in datasheets, except by Diodes Inc. for their ultra-low VCE(sat)"super beta" transistors with very high Beta or hFE. These patented designs have low RCE(sat)=VCE(sat) / Ic . I will not detail thermal effects in detail, except to note that diodes and BJTs are neg. tempco. or NTC and run faster with lower resistance when hot. This is a natural characteristic, though not a recommendation to run them hot. Meanwhile, Vce(sat) vs temp is more complex with Ic and hfe. being somewhat parabolic.

Facts
The actual saturation region is a quadratic zone between the linear Rce and any chosen corner curve asymptote of the constant Ib curves. Beyond this is normally called the active region for amplification with the best linearity. It should be noted that this online plot had very small collector currents, and the so-called collector leakage currents do not show up. They manifest as the slightly elevated slopes pointing backwards to Dr. Early's intercept voltage, projected to fictitious negative voltages where Ic=0 and is known as the "Early Effect" or just Rce leakage resistance.

The choice of the corner depends on your tolerance for THD or total harmonic distortion from the nonlinear behaviour at low Vce. This corresponds to a full-swing negative peak at the collector. For high-power amps, a minimum Vce of 2V is recommended to avoid high current distortion, but for a switch, this would be a lossy operating point. Therefore, for switches, RCE(sat) is computed from the datasheet limits, projecting the current to estimate Pd max.
Pd(sat) = VCE(sat)×IC.

An interesting application of the saturation zone is shorting the base-collector nodes as a diode, where the collector current still follows Vbe and amplifies Ib but with lower hFE values. The Ic/Ib ratios used to define VCE(sat) range from 10, 30, 50, to 100, with 10 being the most common and higher ratios for superbeta types (hFE 300 to 3000+). However, very high beta and low Rce come with higher capacitance and increased noise unless gold-doped, leading to higher prices than standard BJTs.

Standalone transistor amplification is not highly linear; some transistors are more linear than others and are used in audio or power amplifiers. However, feedback can significantly reduce nonlinearities to acceptable levels.

It is easy to achieve 10% distortion on any H-biased amplifier in full-swing by measuring the difference in ±Vpk/Vavg * 100% closely approximates %THD from non-linearity.

Here is another definition of the Saturation Zone where Vcb>0 is forward biased. This imples Vce<= Vbe which contradicts the plot above when Vce=2V with AC distortion threshold at max. DC current as you would not operate Vbe at 2V. There are differences in the transistor models for Rce, Rcb, and Rbe that are not as big as the current gains and this is why Vce saturation region voltages are extended to more linear Active region.

Now getting back to a rephrased version of the original question.

Where is large swing pulse voltage delay the worst? Saturated region or Active Region?

Clue: Where is RC=Tau highest? Which parameters affect C and which affect the effective output impedance? Vbe, Rce, Vce, Vbe, Reverse recovery time model, etc...?


Hint: the biggest effects are reverse recovery from full saturation and then Miller effects dominate due to junction capacitance between collector-base.
Since C maximizes towards PN junction=0V and onward into the forward-biased region this is when Vce reduces to Vbe and is typically < 0.7.
Thus avoiding as much of the Saturation Region as possible at the expense of heat rise, improves pulse delay time and rise time.

The plots discussed so far was for a common emitter (CE), which trades off BW with gain. So naturally configurations like CB and CC are faster for switching and current mode switching is by far faster than voltage mode switching as in ECL, CML.

Conclusion
Lowest CC pulse delays avoid saturation region as much as possible with the minimum as @dick_freebird suggested.

 

[yefj]

Hello, i have tried to recreate the sweep plot for the 2N2369 NPN as Tony described. But still i have dificulty to see mathematickly the start and the end of the saturation region in my plot.

How can i see the exact region of saturation in my plot?
Thanks.

 

[danadakk]