[SOLVED] Test-bed Propagation Delay

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taranom1

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Hi all,
Is the propagation Delay measured for the whole test bed or for the circuit alone ,usually?
I mean that Should I remove buffers and Cloads of test-bed for measuring delay in circuit alone (circuit under test)mode? Detailed Image have been attached.

 

Is the propagation Delay measured for the whole test bed or for the circuit alone ,usually?

This depends only on your measurement statement: you always define the [delay] measurement from a certain node to a (different) certain node, including their respective start/stop voltage levels.

(H)SPICE Example:
Code:
.MEAS TRAN Tdelay TRIG V(in) val=2.5 TD=TDval FALL=1 TARG V(out) val=2.5 FALL=2
From HSPICE_User Guide_Simulation and_Analysis_Version_E-2010.12_December_2010.webloc" SYNOPSYS: HSPICE® User Guide: Simulation and Analysis Version E-2010.12, December 2010, p. 946-947

 
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This depends only on your measurement statement: you always define the [delay] measurement from a certain node to a (different) certain node, including their respective start/stop voltage levels.

Thanks for the answer, Should I remove buffers and Cloads of test-bed in circuit alone mode or they will remain and I should measure from after input buffers to before output buffer? I want know the usual way article writers use.
 

You don't need to remove the buffers/Cloads, just define the measurement statement from where to where.
 
You should declare, or characterize a relevant span of,
output loads and input transition times. Take your cues
from what you find in timing models that already exist for
your technology as far as fanout loading and any input
behavior "box".
 

Thanks all of you!
 

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