Temperature effects in CMOS designs

Explanation 1:
When you increase the temperature, vibration in silicon lattice increases which also increases the number of free electrons and holes which gets freed from their respective bonds due to thermal energy. These free electrons and holes contribute to congestion which decreases the mobility and hence more voltage is required to generate inversion layer in MOSFET (VTH increases).

Explanation 2:
When temperature increases the thermal energy of the electron increases and hence more electron hole pairs are generated. Also the electrons have more energy and hence their mobility increases until a certain value. This leads to decrease in the threshold voltage as there are more minority carriers present making the formation of the channel easier.

Can any one kindly explain which one is correct??


I know that as temperature increases the delay will increase & also i came to know that below 65nm tech. node there is temperature inversion phenomenon, which will decreases delay as temperature increase.
Also i need to know about the mobility variations when the temperature is varying.
Is this delay is depending on the mobility?
Can i anyone explain about the root cause for that??
I mean the Physical reason. Is it because of lattice vibration variation?


Thanks in advance.