TB error

[Kgonz]

Hi all im trying to write a test bench for a SPI Slave module i made but i keep getting a bug saying expecting function or procedure or impure or pure at line 11

below is a copy of my TB

library IEEE;
use IEEE.std_logic_1164.all;
entity Spi_practice2_tb is
end Spi_practice2_tb;

architecture bench of Spi_practice2_tb is

component SPI_SLAVE1
    generic(
        WORD_SIZE : natural := 8;
        );
    port(CLK,RST,SCLK,CS_N,MOSI,DIN_VLD: in std_logic;
         MISO,DIN_RDY,DOUT_VLD: out std_logic;
         DIN: in std_logic_vector;
         DOUT: out std_logic_vector);
end component;

signal CLK,RST,SCLK,CS_N,MOSI,DIN_VLD: std_logic;
signal MISO,DIN_RDY,DOUT_VLD: std_logic;
signal DIN: std_logic_vector;
signal DOUT: std_logic_vector;
constant clock_period: time := 10 ns;
signal stop_the_clock:boolean;
constant BIT_CNT_WIDTH : natural);

    signal sclk_meta          : std_logic;
    signal cs_n_meta          : std_logic;
    signal mosi_meta          : std_logic;
    signal sclk_reg           : std_logic;
    signal cs_n_reg           : std_logic;
    signal mosi_reg           : std_logic;
    signal spi_clk_reg        : std_logic;
    signal spi_clk_redge_en   : std_logic;
    signal spi_clk_fedge_en   : std_logic;
    signal bit_cnt            : std_logic;
    signal bit_cnt_max        : std_logic;
    signal last_bit_en        : std_logic;
    signal load_data_en       : std_logic;
    signal data_shreg         : std_logic_vector;
    signal slave_ready        : std_logic;
    signal shreg_busy         : std_logic;
    signal rx_data_vld        : std_logic;


begin
PM: entity work.SPI_SLAVE1
    generic map
    (WORD_SIZE => 8
     );
port map (CLK => CLK,
      RST => RST,
      SCLK => SCLK,
      CS_N => CS_N,
      MOSI => MOSI,
      DIN  => DIN,
      DIN_VLD => DIN_VLD,
      MISO => MISO,
      DIN_RDY => DIN_RDY,
      DOUT => DOUT,
      DOUT_VLD => DOUT_VLD);

process
begin
RST <= '1';
wait for clock_period;
spi_clk_fedge_en <= '1';
cs_n_reg <= '0';
wait for clock_period;
DIN_VLD <= '1';
cs_n_reg <= '1';
rx_data_vld <= '1';
wait;
end process;

process -- clock generation
begin
while not stop_the_clock loop
CLK <= '0';
wait for clock_period / 2;
CLK <= '1';
wait for clock_period / 2;
end loop;
wait;


end process;
end;