Synthesizing Matlab code to FPGA

[echo47]

Matlab to FPGA

A FLEX 10K doesn't have embedded multipliers. That could be a big handicap. How many taps does your FIR filter require? How many bits wide is your data? How fast is the data?

If your data is relatively slow, be sure to disable "parallel" architecture in fdatool. Parallel computes the entire FIR sum-of-products in one clock cycle, and consumes a lot of logic. Sequential architecture is much smaller, but takes many clock cycles.

21% of what size FLEX 10K?

 

[rsrinivas]

Matlab to FPGA

Is it a 4 tap filter.4 mul's 4 add's.(this only constitutes 8K gates approx say 16 bit)which is pretty bad 4 an FPGA without mul's and add's i think.
can u just synthesise a verilog code for the same parameters u have used for the VHDL code.
actually matlab is concentrated on VHDL than verilog.so u can compare them in terms of resource usage and clk speed.

 

[lawrence_idol]

Re: Matlab to FPGA

hi echno and rsinivas,

My project locked into FLex 10k DEVICE which has 1152 LE and 2304 LE for UP2(another flex10K).
what i think is.. even this is an old device but i still can try my best implement a filter with it..a design vision.
My project never state any filter specification..
but the thing is.. it jus mention mix 5v sine wave + 3 v noise feed into ADC then to FPGA afterall filter out noise and regain 5v sin wave at the DAC output.
maybe you guys would know to figure out wat type of filter it might be.
thanks in advance
best regards
lawrence

 

[echo47]

Matlab to FPGA

Hi lawrence_idol, You probably want an IIR filter, because it will be much smaller than an equivalent FIR filter. For example, I used MATLAB's fdatool to design a 2nd-order Butterworth IIR bandpass filter with a center frequency of 1kHz, a bandwidth of 10Hz, and a sample rate of 10kHz. I selected 16-bit quantization, and then generated HDL with MATLAB's CSD method instead of regular multiplier method (I'm pretending that my FPGA doesn't have hardware multipliers). By the way, MATLAB's HDL Coder forces "fully parallel" architecture with IIR filters, and that's wasteful if you don't need blazing speed. Finally, I used Xilinx ISE to synthesize the HDL into a tiny XC3S50 Spartan-3 FPGA. With default optimizations, the filter consumed about 1/3 of the device. I don't know how the size of the XC3S50 compares to your Altera FPGA.

 

[rsrinivas]

Re: Matlab to FPGA

noise will consist of all frequency components.
ur 5v sine wave is of wat frquency?
say u have a pure 500 hz sine wave u can use a bpf with 475 and 525(or considering the feasibilities)
and ur output should be as expected with some noise(negligeable).
u can verify this...
after u design ur filter export the filter as filter object to workspace.
use randn fuction to get noise samples.
then filter it with the filter object.
y = filter(Hd,x)
Hd --> filter object
x --> noise samples
plot y.
u should see a sine wave as expected.

Added after 5 minutes:

hi alvdb
check this out