Synthesis with blackbox in Genus

[artecoll]

Hi everyone. Might be someone knows answer for my question.
I have an HLB and he contains some macros. I want run synthesis with blackbox. I know, that we can set attributes hdl_error_on_blackbox and init_blackbox_for_undefined and find the name of module or macro, which created as blackbox, after elaborating (for example, command check_design). But can i define a name of macro or module, which i want use as blackbox, before elaborating and indicate to the tool that such module should be created as blackbox?

 

[ahsrabrifat]

In Verilog, you can use the black_box attribute to specify a module as a black box:

(* black_box *)
module my_macro (...);
endmodule

In VHDL, you can use black_box synthesis directives:

attribute black_box : string;
attribute black_box of my_macro : entity is "true";