shaiko
Advanced Member level 5
I'd like to share my FIFO design that uses an extra bit (MSB) to generate control flags.
I've chosen this approach because it can be used for both synchronous and asynchronous (with adjustments) FIFOs.
Would you change anything in the code ( while still maintaining the extra bit concept ) ?
I've chosen this approach because it can be used for both synchronous and asynchronous (with adjustments) FIFOs.
Code:
signal write_pointer , read_pointer : unsigned ( a downto 0 ) ;
signal write_address , read_address : unsigned ( a - 1 downto 0 ) ;
signal almost_full_threshold , almost_empty_threshold : unsigned ( a - 1 downto 0 ) ;
signal almost_full , full , almost_empty , empty : std_logic ;
signal msb_equal , pointer_equal : std_logic ;
pointer_equal <= '1' when write_pointer = read_pointer else '0' ;
almost_full <= '1' when empty = '0' and read_address - write_address <= almost_full_threshold else '0' ;
full <= '1' when address_equal = '1' and pointer_equal = '0' else '0' ;
almost_empty <= '1' when full = '0' and write_address - read_address <= almost_empty_threshold else '0' ;
empty <= '1' when pointer_equal = '1' else '0' ;
writing : process ( clock , reset ) is
begin
if reset = '1' then
write_pointer <= ( others => '0' ) ;
elsif rising_edge ( clock ) then
if write_request = '1' and full = '0' then
write_pointer <= write_pointer + 1 ;
end if ;
end if ;
end process writing ;
reading : process ( clock , reset ) is
begin
if reset = '1' then
read_pointer <= ( others => '0' ) ;
elsif rising_edge ( clock ) then
if read_request = '1' and empty = '0' then
read_pointer <= read_pointer + 1 ;
end if ;
end if ;
end process reading ;
Would you change anything in the code ( while still maintaining the extra bit concept ) ?