Synchrbuck converter without reverse current detection exists?

[treez]

For example, a sudden full-load-to-no-load-transient, where the output sours upwards and gives an overvoltage (overshoot) which lingers, and in the process causes the error amplifier to rail low....not permanently but just till the feedback loop gets its act together and stabilises to the new load level....that interval of railed error amp lowness could end up with an overcurrent surge in the sync fet.

 

[Warpspeed]

In that case, as there is now no load on the output, turning on the lower mosfet will just pull the output back down to where it should be.

Current through this mosfet will ramp down and then reverse, discharging the output capacitor back to where it should be.

All pretty violent, but it should not let the smoke out.

The scenario mentioned earlier of being connected to a battery, there cannot ever be a sudden transition from full load to zero load. Think about it..

 

[mtwieg]

For example, a sudden full-load-to-no-load-transient, where the output sours upwards and gives an overvoltage (overshoot) which lingers, and in the process causes the error amplifier to rail low....not permanently but just till the feedback loop gets its act together and stabilises to the new load level....that interval of railed error amp lowness could end up with an overcurrent surge in the sync fet.

In this case the peak current seen by the lower FET is easy to calculate. At worst, all the excess energy in the capacitor will be transferred to energy in the inductor. So ((Vmax²-Vmin²)*Cout/L)½=Imax. For reasonable component values, Imax won't be huge.

 

[Warpspeed]

In this case the peak current seen by the lower FET is easy to calculate. At worst, all the excess energy in the capacitor will be transferred to energy in the inductor. So ((Vmax²-Vmin²)*Cout/L)½=Imax. For reasonable component values, Imax won't be huge.

My thinking too.
It will just ring back down to normal output voltage, and the drama will be over.

 

[treez]

In this case the peak current seen by the lower FET is easy to calculate. At worst, all the excess energy in the capacitor will be transferred to energy in the inductor. So ((Vmax²-Vmin²)*Cout/L)½=Imax. For reasonable component values, Imax won't be huge.

as per page 14 (top) of the lm25115 sync buck datasheet, that could end up with the output voltage going negative which could damage the load
https://www.ti.com/lit/ds/symlink/lm25115.pdf

 

[FvM]

The error of reasoning is to think that a protection means which may be necessary for a specific application would be necessary for all others too. Like building a dike around your house on the hill because your neighbour in the valley has it.

- - - Updated - - -

On the other hand, it's no harm to have overcurrent protection for both high- and low-side transistors. If the switcher topology can provide it without much extra effort, you should implement it.

 

[treez]

its interesting, because I've never actually seen it defined when you do, and when you don't , need reverse current sensing in the sync FET of a sync buck converter. I take it from our discussions here that battery charging applications always do need reverse current sensing in the sync FET.
Also that applications with a large output capacitor do need reverse current sensing in the sync FET.
Also, from page 14 (top) of the LM25115 datasheet, any application that has a load that may be damaged by a reverse polarity input does need reverse current sensing in the sync FET.

LM25115 datasheet
https://www.ti.com/lit/ds/symlink/lm25115.pdf

 

[treez]

I think we will all agree with the following…
As the attached LTspice simulation shows, if a Sync Buck is done in such a manner that the sync FET can remain permanently ON for longer than one switching period, then that is very very bad and should not be done.

Do you also agree that Sync Bucks have AC current in the current sense transformer (when on no-load or light-load), and so the current sense transformer needs to have the Diode/Zener bit in it as shown. (as well as the 33k resistor for transformer reset)

The weakness of the attached circuit, is that it simply has no means to accurately ensure that the sync FET never stays ON for more than one switching period. This circuit was sent to us from a consultancy and they didn’t tell us about this circuit’s weakness. You can see that the sync FET gets held on for more than one switching period even when the error amplifier output voltage is “not” railed low. (in no-load)

 

[treez]

Hello,
The attachd Sync Buck LTspice simulation (pdf schem also shown) shows why reverse current sensing is absolutely needed in the sync FET of any Sync Buck converter……
If you run the simulation, you see that it is perfectly stable in full load…then at 4ms, it goes into no_load, and then goes totally unstable with overly high inductor currents repeatedly occuring….you can actually see the way that the reverse current in the sync FET “staircases” upwards to dangerous levels. (and LTspice doesn’t even simualte saturation in inductors so it would be worse than seen here)

This prooves that reverse current sensing in the Sync Fet of a sync Buck converter is definetely needed. We cannot just blame instability, as this Sync Buck is perfectly stable in full-load.
It is the Sync Buck’s capacity to go unstable in no_load that means that you absolutely MUST have reverse current sensing in the sync FET of a Sync Buck Converter.
I rest my case.

You can actually see that in no_load, the duty cycle of the main fet becomes extremely small, (as you’d expect) and since the duty cycle of the sync fet is the “NOT” of that, then the duty cycle of the sync FET gets very large…and so during the long ON time of the sync FET, the reverse current builds up in the sync FET……the main FET only switches on for a small time interval, and does not sufficiently stop the high current flow because it occurs within its “leading edge blanking time” (or rather in the “delay time of the current sense filter” in this case)…thus the inductor current “staircases” up to dangerous levels, and this is seen as the reverse current flow in the sync FET. This problem would not happen if their was reverse current sensing in the sync FET.

As such, ALL Sync Buck Converters need reverse current sensing in the Sync FET. An absolute "MUST have" feature.

 

[Easy peasy]

Certainly under discontinuous operation the fet must be off, when an equivalent diode would be off, else you will get reverse currents, there are some good synch buck control IC's out there that incorporate this into their structure...

 

[treez]

Thankyou, and it is simply not possible for the controller to "know" if DCM has been reached unless their exists reverse current sensing in the sync FET.

(By DCM, I mean cases that "would be DCM if their was no sync FET", because as you know, a sync FET buck never goes into DCM as its inductor current just becomes AC when in no-load.)

 

[Dan Mills]

But actually there ARE circumstances under which a CCM converter can actually be designed to run both positive and negative average current, sometimes you actually do need this.

What you have proved is that THAT particular design is broken, not that you always need low side current sense.
LT1243 is probably not really intended for a sync supply, at least not for one so simple minded.

Regards, Dan.

 

[treez]

But actually there ARE circumstances under which a CCM converter can actually be designed to run both positive and negative average current, sometimes you actually do need this.

I agree, and that is where reverse current sensing in the sync FET is done, so as to guard against overly high reverse current in the sync FET of the sync buck converter.
It is never wanted to run negative "average" current in a sync Buck, that would equate to steady current flow from load to source.
You can have current going from load to source at times, but not "average" current going from load to source...not in a sync buck.....if you are using a sync buck and you have average current flow from load to source, then your sync buck is behaving like a boost converter going the opposite way to the sync buck.

- - - Updated - - -

If a Current Mode NON-Sync Buck goes into no_load, then it usually goes unstable…this is due to the fact that the load pole (1/2.pi.R.C) becomes very low frequency. However, this does not usually matter, because usually the output capacitor is large and the effect of this instability on the output voltage is insignificant.
Now, if a Sync Buck goes into no_load, then it often goes unstable for exactly the same reason as the NON-Sync Buck. The problem is that a Sync Buck in no_load is capable of drawing large currents out of the output capacitor in short intervals of time…..so the instability in no_load of a Sync Buck can result in severely erratic performance and wild swings in V(out).
-However, if one has reverse current sensing in the Sync Buck FET, then the Sync Buck in no_load can be adequately controlled no problem.

However, if there is no reverse current sensing in the Sync FET of a Sync Buck, and you go into no_load, then you can stand by!….only a very unwise engineer would deliberately allow this to happen.

 

[treez]

Coming back to the subject of Synchronous Buck converters that don’t have reverse overcurrent sensing in the Synchronous FET, and re-affirming that this is a totally bad situation….

The TPS40055 and the LM25115 are both ti.com chips(sync buck controllers) . Page 14 of the LM25115 datasheet tells why reverse overcurrent sensing in the synchronous FET is needed.

The TPS40055 looks like being a bogus control chip, it doesn’t have the necessary reverse overcurrent sensing. Its close neighbour, the TPS40054 , does sense for zero current in the Sync FET and actually disables the synchronous FET when that happens.

Does anyone know of a current ti.com email address that can be used to clear this issue up?

LM25115 datasheet
https://www.ti.com/lit/ds/symlink/lm25115.pdf

TPS40055
https://www.ti.com/lit/ds/symlink/tps40055.pdf


Any synchronous Buck controller MUST have the facility to disable the Synchronous FET when in light load and the inductor current becomes bi-directional. Either that, or it must have reverse overcurrent sensing in the synchronous FET.
The TPS40055 has neither of these facilities, and will just switch the synchronous FET right down to no load. The TPS40055 appears to be a bogus chip.

Easy Peasy, in post #30 above, confirms his support that the sync FET of a synchronous Buck should be turned OFF for those times when an equivalent diode of a "non sync buck" would not be conducting.