Switch Delay and settle delay

[mishrashashi]

Dear all,
I have posted the same question long back in forum

https://www.edaboard.com/threads/213818/

I didn't get answer:!:. Lets disscuss here


How to calculate Switch delay and settle delay in signal integrity?

 

[cks3976]

Switch time is commonly refered to Rise or Fall time of a signal. There are various definitions for this time. The one I follow is "this is the time taken by a signal to reach 90% of its peak voltage level starting from 10%" Fall time is the converse of this. Rise time or Fall time is affected in a PCB mainly by loading on a driver. In constraint manager you can put a cap on this value, which inturn will put a cap on maximum trace capacitance.

Settle delay is the time taken by a signal to settle down in it's permissible peak or least voltage level after reaching that level.