[SOLVED] "subc" terminal = substrate contact. (IBM process). LVS error.

[dgnani]

Hi Palmeiras

the script is needed to overcome limitations of Cadence CDL netlister, which is used by Calibre to generate the schematic netlist and has a hard time dealing with things like 3 terminal resistors

as of GRLOGIC if you do not use it (which I recommend) the switch you mention is irrelevant

as of SXCUT:drawing, it is a layer used to name different part of the substrate with different names, it makes only sense if the different substrates are actually (somewhat) physically isolated by guardrings, people instead often use it because they cannot figure out how to work with subc and in that case it prevents LVS to identify real issues like soft-connect violations e.g. a badly connected PNP collector

 

[nana_7488]

are you post-processing the schematic netlist according to the IBM LVS documents (cdl_processor.pl)?

if not: add the postprocessing script under preferences>Trigger>pre-execution...

if yes: please post (or PM) the complete netlist of this cell so I can study it better

---------- Post added at 09:26 ---------- Previous post was at 09:24 ----------



using SXCUT:drawing layer is usually a bad idea unless there are physical substrate isolation structures (e.g. guard rings), can you post the LVS result w/o SXCUT:drawing layer?

Hi dgnani


This is my LVS report without SXCUT layer.Hope you can help me especially with the soft substrate pin errors. Thanks.

**************************************************************************************************************
INCORRECT NETS

DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************

1 ** missing net ** X_NAND1/N$42


**************************************************************************************************************
INCORRECT INSTANCES

DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************

2 ** missing instance ** X_NAND1/X1 subc



**************************************************************************************************************
INCORRECT SUBSTRATE CONNECTIONS

DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************

3 M0(-1.130,5.730) M(lvtnfet) X_NAND1/M_X2 M(lvtnfet)
b: 8 ** X_INV1/N$40 **
** missing net ** b: X_NAND1/N$42

--------------------------------------------------------------------------------------------------------------
4 M1(0.400,5.730) M(lvtnfet) X_NAND1/M_X3 M(lvtnfet)
b: 8 ** X_INV1/N$40 **
** missing net ** b: X_NAND1/N$42

 

[dgnani]

it looks like you are using an extra subc device in the schematic (X_NAND1/X1), can you eliminate that and rerun LVS?

 

[nana_7488]

it looks like you are using an extra subc device in the schematic (X_NAND1/X1), can you eliminate that and rerun LVS?

Hi dgnani

my topcell design is AND2 gate, based on NAND2 gate and INV gate. If i eliminate the subc in NAND, the LVS for NAND gate will have an error.

 

[dgnani]

if you have another subc at a different level then eliminate that one

 

[palmeiras]

Hi dgnani,

Thanks again for your help!
Ok! In order to finish our discussion, what is the other way (therefore avoiding SXCUT - as you´ve suggested) to make the tool understand that all subc devices are connected?
Backing to the initial problem, I can not connect the subc of the two inverters (it has four pins: vdd, gnd, input, output) because it is not allowed to have a pin in the bulk terminal.
Why? Because if I add a pin in the bulk terminal, there is a conflict because there will be two pins with different names in the same net, that is: bulk and gnd. And Assura does not permit it.

What do you usually do in order to solve this?

Best regards.

 

[jimito13]

It is allowed to have a pin in your symbol that corresponds to the substrate.
So suppose that you have a top level schematic and several sub-blocks :

--All sub-blocks will have their own subc in the schematic and lots of sub contacts in the layout.
--At the schematic of each sub-block (and consequently at the symbol) you will have a pin named SUB (for example but avoid the global sub!) and at the layout this pin should be stamped with SXCUT label layer.
--All these individual substrate pins should terminate at the final subc (at it's proper substrate side) of the top-level.

Unfortunately you must use SXCUT for this case and it is a little bit bothering since you PDK doesn't have LVS Marker.
With LVS Marker and some combinations of this you can avoid all these special and annoying layers like SXCUT.

 

[dgnani]

Hi dgnani,

Thanks again for your help!
Ok! In order to finish our discussion, what is the other way (therefore avoiding SXCUT - as you´ve suggested) to make the tool understand that all subc devices are connected?
Backing to the initial problem, I can not connect the subc of the two inverters (it has four pins: vdd, gnd, input, output) because it is not allowed to have a pin in the bulk terminal.
Why? Because if I add a pin in the bulk terminal, there is a conflict because there will be two pins with different names in the same net, that is: bulk and gnd. And Assura does not permit it.

What do you usually do in order to solve this?

Best regards.

There is no need to have a pin to connect the substrates of different instances as long as you use inherited connections for the substrate:
- if you use a subc device connect the bottom to a net called [@substrate:%:sub!] (net expression of property name 'substrate' and default value 'sub!')
- if you use subcx this connection is already done for you

the other side of your subc is already connected to the gnd pin so there is no problem for that

Let me know if this is not clear

---------- Post added at 10:42 ---------- Previous post was at 10:41 ----------

It is allowed to have a pin in your symbol that corresponds to the substrate.
So suppose that you have a top level schematic and several sub-blocks :

--All sub-blocks will have their own subc in the schematic and lots of sub contacts in the layout.
--At the schematic of each sub-block (and consequently at the symbol) you will have a pin named SUB (for example but avoid the global sub!) and at the layout this pin should be stamped with SXCUT label layer.
--All these individual substrate pins should terminate at the final subc (at it's proper substrate side) of the top-level.

Unfortunately you must use SXCUT for this case and it is a little bit bothering since you PDK doesn't have LVS Marker.
With LVS Marker and some combinations of this you can avoid all these special and annoying layers like SXCUT.

not the best strategy...

 

[jimito13]

not the best strategy...

I absolutery agree with you dgnani,i wouldn't do that as well but i mentioned it "just for history" since palmeiras was wondering.

 

[palmeiras]

HI dgnani and Jimito,

Thank you very much for the interesting discussion.
(a) I believe that dgnani´ve pointed out the best solution: to use inherited connections.
I´m not using them, and now my design is lvs clean in Assura and Calibre. But, in order to have it clean with Calibre I was forced to use SXCUT layer. In summary, there is different ways to solve this issue.
(b) It not possible to have two pins in the same net. Therefore, using a symbol with a pin related to the substrate can cause more problems.

Thanks again, guys.
Best Regards.

 

[dgnani]

HI dgnani and Jimito,

Thank you very much for the interesting discussion.
(a) I believe that dgnani´ve pointed out the best solution: to use inherited connections.
I´m not using them, and now my design is lvs clean in Assura and Calibre. But, in order to have it clean with Calibre I was forced to use SXCUT layer. In summary, there is different ways to solve this issue.
(b) It not possible to have two pins in the same net. Therefore, using a symbol with a pin related to the substrate can cause more problems.

Thanks again, guys.
Best Regards.

Just to be clear using SXCUT:drawing to get this LVS 'clean' is an artificial solution that will let you get away with serious soft-connect violations;
There is no problem adding a substrate pin in the symbol of your gates (it has to be stamped in SXCUT:label), which is a more cumbersome solution than using inherited connections but it is still better solution than artifically cutting the substrate with SXCUT:drawing

 

[Electromagnetic Dave]

Hi all,

I believe I am having a similiar issue. I'm trying to get a 6T SRAM cell layout Assura LVS clean using the cmrf7sf PDK. The schematic is a 6T cell with pin Vdd connecting to the pMOS sources and substrates, pin BL,~BL,WL connected as appropriate, and a pin for gnd connected to the sources of the pulldown nMOSes as well as the subc IBM component. The DRC check comes back clean, but LVS returns this:

*******************************************************************************
****** cell schematic mySRAM <vs> cell layout mySRAM
*******************************************************************************

Reduce Statistics
================= Original Reduced
Cell/Device schematic layout schematic layout
(nfet) Generic 4 4 4 4
(pfet) Generic 2 2 2 2
(subc) Generic 1 2* 1 1

Match Statistics
================ Total Unmatched
Cell/Device schematic layout schematic layout
(nfet) Generic 4 4 0 0
(pfet) Generic 2 2 0 0
(subc) Generic 1 1 0 0
------ ------ ------ ------
Total 7 7 0 0

Match Statistics for Nets 9 8 1 0

=========================================================================[cell]
====== Bad Initial Net Bindings (nets don't match) ============================
===============================================================================

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (badbind 1)
Schematic Net: sub!
S 4 of nfet B

Layout Net: sub!
L 4 of nfet B
L *1 of subc sub

=========================================================================[cell]
====== Unmatched Internal Nets ================================================
===============================================================================

S ?_unconnected_0


=========================================================================[cell]
====== Problem Schematic Nets (no exact match in layout) ======================
===============================================================================
S
S ?sub!
S 4 of nfet B
S
S ?_unconnected_0
S 1 of subc sub

=========================================================================[cell]
====== Problem Layout Nets (no exact match in schematic) ======================
===============================================================================
L
L ?sub!
L 4 of nfet B
L 1 of subc sub

=========================================================================[cell]
====== Summary of Errors ======================================================
===============================================================================

Schematic Layout Error Type
--------- ------ ----------
1 1 Bad Initial Net Bindings
1 - Unmatched Internal Nets

I've tried adding a sub! SXCUT:label label to a blank area of the substrate, surrounding that with a rectangle of sub:drw, adding a pin named sub! using the SXCUT:drw, AND using the NO_SUBC_IN_GRLOGIC switch in the LVS run. None of these things have caused the above to go way. Any suggestions would be appreciated. Thanks!

 

[dgnani]

Hi Dave

I am not an Assura user but if read the log file correctly, for that LVS run what was missing was a connection between the NFET:B terminal and the subc:sub terminal in the schematic...

Using GRLOGIC to suppress subc extraction has the side effect to suppress some DRC rules, which is ok for digital but not for analog designs, in your case I would stick with analog rules, given the swings involved and matching requirements particularly in th read phase.

Keep us posted, this should be easy to debug

 

[Electromagnetic Dave]

It was very easy to debug, after a day off. I grepped the LVS run directory for "sub!" and found the following two lines in the log file:

*WARNING* Programable terminal sub on I3 in cell cell schematic mySRAM, No property 'sub'.
*WARNING* Connection error: The instTerm. sub!, on instance I3 in cell cell schematic mySRAM does not have a corresponding terminal in the master, subc.

The relevatory line, however, was a few above these:

"Net Listing Mode is Digital"

When setting up my .bashrc file, I hadn't capitalized "analog" in what should have been

CDS_Netlisting_Mode="Analog"

That's fixed now and the layout's coming back LVS clean - with and without the substrate label. After some panicky resimulations of my previous schematic work, I'm moving on to performing an extraction - which I understand the cmrf7sf PDK also has some known issues with, which are dealt with in a separate thread in these forums. Thanks for your help!

 

[kaushikmazumdar]

Hi palmeiras,

Can you explain how the subc connection worked for you.
In my circuit, I have one inverter connected to the gate of a nmos switch. The source and bulk terminal of the nmos are different. While the bulk is grounded, source is connected to output ( basically nmos used as switch here ). How do I do the bulk connection for schematic and layout ?