Strange PLL lock problem?

[cqmyg5]

Hello,

I am testing a 2.4G PLL.
This PLL couldn't lock if just after power-on, and vco free-run at 2480MHz, vtune=0v. When I increse both vco current and vco's tuning cap, the PLL can now lock in 2400M-2490MHz. After this, I decrese both vco current and vco's tuning cap to original value, then the PLL also can lock 2400M-2490MHz.

Why the PLL could lock after it has been increased and then decreased current and cap, since the value is as same as it's just after power-on?

Thanks!

 

[Analog_starter]

For a PLL circuit, you must check its loop characteristics.
Matlab is a good choice.

 

[purefen]

Dear:
The pfd output should be checked first. IF the pfd work correctly, the vtune should be raise. Because u say that ur vtune is always zero after power on.