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AFAIK, yes, there is indeed: Stamping means attaching a fixed layout node name, e.g. to substrate or an isolated nwell, i.e. all regions which actually are electrically resp. physically connected in layout (in real silicon).
A soft connection of two or more schematic nodes (with different node names, of course) still allows a successful LVS run, if these nodes are actually electrically (resp. physically) connected, like, e.g., analog and digital supply nodes with different schematic names (agnd & dgnd, avdd & dvdd), which anyway are connected electrically and/or physically on chip.
So such soft connected schematic nets can match with an electrically common stamped layout net.
The advantage of this method is that you don't need an extra schematic view for LVS with a single node name for schematic nets which are electrically connected anyway on chip, to achieve a successful LVS, resp. an extra layout view with isolated stamped (e.g. substrate) regions for the same purpose.
From what I have seen and know about this, if, say digital and analog ground nets - agnd and dgnd - are connected through the metal layers (with "low" resistance), then people place dummy intended metal resistors, with very resistance, between these nets, to allow LVS to treat them as different nets even though they are electrically connected.
Soft connection ("sconnect" in Calibre SVRF) is used to connect to highly resistive layer shapes - such as wells - so that different nets may be connected to the same well, but their connectivity information is not passed to each other through the highly resistive wells. Again, even though these different nets are electrically connected to each other, soft checks allow LVS to treat them as separate nets, without any errors and problems. In "sconnect", connectivity is uni-directional, and connectivity information is passed form upper layers to lower layers only (not the other way around).
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